Manufacturing method for structure of extremely thin silicon on insulator and manufacturing method for semiconductor device

Abstract

Disclosed are a manufacturing method for a structure of extremely thin silicon on an insulator (ETSOI) and a manufacturing method for a semiconductor device. The manufacturing method for the semiconductor device includes: providing silicon on insulator (SOI); forming a hard-mask layer on a top-silicon layer and carrying out a patterning processing on the hard-mask layer; and measuring real thicknesses of exposed areas of the top-silicon layer; injecting doping ions into the exposed areas of the top-silicon layer with an injection quantity related to corresponding real thicknesses of the injected areas; carrying out an etching processing, and removing part of the exposed areas of the top-silicon layer and forming trenches; forming side walls on flanks of the trenches and forming gate structures on areas defined by the flanks; carrying out a planarization processing so that upper surfaces of the gate structures are flush with an upper surface of the hard-mask layer; removing the hard-mask layer; and injecting ions into the exposed areas of the top-silicon layer and forming elevated source/drain areas. The manufacturing method for the structure of the extremely thin SOI and the manufacturing method for the semiconductor device enable the thicknesses and uniformity of the areas of the top-silicon layer on the extremely thin SOI structure to be controlled precisely so that damages on the top-silicon layer are prevented.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing an ultra-thin silicon-on-insulator structure and a method for manufacturing a semiconductor device including the ultra-thin silicon-on-insulator structure. Background technique [0002] With the development of semiconductor technology, the integration level of integrated circuits is getting higher and higher, and the feature size (CD) of devices is getting smaller and smaller. When the feature size of the device is reduced to deep submicron (under 0.25 micron is called deep submicron), the leakage current of the device increases, the drain induction barrier lower (DIBL, Drain induction barrier lower) effect and the short channel effect (SCE) etc. are becoming more and more obvious, and become the main problem to be overcome in reducing the size of the device. [0003] Semiconductor devices with FDSOI (Fully Depleted Silicon On Insulator, fully d...

AI Technical Summary

Problems solved by technology

Due to the uneven and uncontrollable thickness of the top silicon layer 20 of the ETSOI structure in the prior art, the performance of the semiconductor device is affected

[0018] Even if the top silicon layer 20 in the semiconductor device is uniform and controllable, the etching process when forming the spacer 25 is likely to etch away all or part of the top silicon layer 20, so that the insulating layer 21 (that is, silicon oxide) cannot be formed. Silicon is epitaxially grown to form raised source 26 and raised drain 27

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