Linear equalizer

A linear equalizer, inverter technology, applied in baseband system components, shaping networks in transmitter/receiver, etc., can solve the skin effect and transmission medium impedance discontinuity, dielectric loss, bandwidth limitation, etc. problem, to achieve the effect of increasing bandwidth, reducing common mode interference, and improving equalization performance

Active Publication Date: 2013-10-30
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, data serial communications at several Gb/s speeds are limited by bandwidth
The bandwidth limitation is mainly due to dielectric loss, skin effect and impedance discontinuity o

Method used

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  • Linear equalizer

Examples

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Example Embodiment

[0023] Such as figure 2 Shown is a schematic structural diagram of a linear equalizer in an embodiment of the present invention. The linear equalizer of the embodiment of the present invention includes:

[0024] The first MOS transistor 1 and the second MOS transistor 2 form a differential input pair, and both the first MOS transistor 1 and the second MOS transistor 2 are NMOS transistors. The gates of the first MOS transistor 1 and the second MOS transistor 2 are input terminals of a pair of differential input signals inn and inp, respectively, and the drains of the first MOS transistor 1 and the second MOS transistor 2 are a pair of The output terminals of the differential output signals outn and outp, and the sources of the first MOS transistor 1 and the second MOS transistor 2 are respectively connected to a current source.

[0025] A first resistor 14 and a first inductor 15 are connected in series between the drain of the first MOS transistor 1 and the power supply; a firs...

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Abstract

The invention discloses a linear equalizer which comprises a differential input pair pipe, a second resistor, a third MOS capacitor and a fourth MOS capacitor, wherein the differential input pair pipe is composed of a first MOS transistor and a second MOS transistor, the drain electrode of the first MOS transistor and the drain electrode of the second MOS transistor are respectively and sequentially connected with a first resistor and a first inductor in series, and the first resistors and the first inductors are required to produce a zero point higher than channel bandwidth. The two ends of the second resistor are connected with the source electrode of the first MOS transistor and the source electrode of the second MOS transistor respectively. The third MOS capacitor and the fourth MOS capacitor are composed of the MOS transistors connected through the source electrodes and the drain electrodes in a short circuit mode, a grid electrode of the third MOS capacitor and a grid electrode of the fourth MOS capacitor are connected with the source electrode of the first MOS transistor and the source electrode of the second MOS transistor respectively, and the second resistor, the third MOS capacitor and the fourth MOS capacitor are required to produce another zero point higher than the channel bandwidth. The linear equalizer can be used in high-speed serial transmission, the two zero points can be formed, low frequency small transmission gain and high frequency large transmission gain can be achieved, high frequency transmission gain can be greatly improved, and the balancing performance is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a linear equalizer. Background technique [0002] The continuous improvement in the performance of CMOS integrated circuits has made it possible to transmit signals at speeds up to several Gb / s on cables or substrates. However, data serial communications at several Gb / s speeds are limited by bandwidth. Bandwidth limitation is mainly due to dielectric loss, skin effect and impedance discontinuity of the transmission medium. In a bandwidth-limited channel, when the data rate exceeds the bandwidth, the received signal will be seriously distorted due to inter-symbol interference (ISI). In the prior art, an equalizer is usually used in a receiver to compensate or reduce ISI. [0003] Choi et al. disclosed an equalizer in the article "A 0.18-μm CMOS 3.5-gb / s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method", the source of which is: IEEE J...

Claims

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Application Information

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IPC IPC(8): H04L25/03H04L25/02
Inventor 朱红卫刘国军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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