Semiconductor manufacturing method based on self-aligned double-patterning technology
A self-aligned double-pattern and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of low mask layer selectivity, unreasonable mask layer settings, and low yield of semiconductor devices, etc. Problems, to achieve the effect of improving yield and selection rate
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[0032] Next, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
[0033] For the convenience of understanding, the present invention provides a process flow diagram of a specific embodiment, such as figure 2 shown, combined with Figure 3a The process diagram of the manufacturing method of the present invention given in -f is further explained.
[0034] Such as figure 2 and 3a As shown, first, a low-K material or an ultr...
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