Interconnect structure and manufacturing method thereof

Abstract

The invention provides an interconnection structure and a manufacturing method thereof. A carbon nanometer interconnection technology is embedded into a traditional CMOS partial copper interconnection technology, a carbon nanometer tube is used as interconnection materials of partial-interconnection through holes or contacting holes, a grapheme nanobelt is used as partial-interconnection metal wire interconnection materials, the stray capacitance between a parasitic resistor and a connecting wire caused by small partial interconnection size in the copper interconnection technology is greatly lowered, and meanwhile a sealed cavity is used as partial interconnection media, and interlay stray capacitance is effectively lowered. The interconnection structure and the manufacturing method thereof can be compatible with the existing CMOS copper interconnection technology, interconnection RC delay is effectively lowered, chip performance is improved, and chip cost is controlled.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an interconnection structure and a manufacturing method thereof. Background technique [0002] Nowadays, the amount of social information is increasing rapidly, which puts forward higher and higher requirements for information processing, transmission and storage. As the pillar of the information industry, the semiconductor industry, especially the CMOS technology, has been developing at a high speed according to Moore's law, driven by this demand, and has become the fastest growing industry in the past 50 years. [0003] With the rapid development of CMOS technology, the integration level of devices on the chip is continuously improved, and the chip speed is also getting faster and faster. In order to meet the requirements of device integration and speed, Cu interconnection has gradually replaced the traditional Al interconnection and become the mainstream. At the sam...

AI Technical Summary

Problems solved by technology

With the continuous shrinking of the device size, the interconnection delay has surpassed the device-level delay and has become the main factor affecting the operating frequency of the circuit; especially the reduction of the line width makes the electronic transport of the Cu line enhanced by the scattering between the surface and the grain boundary. The resistivity of Cu wire below 100nm rises sharply, which will greatly affect the performance of the circuit

The use of low dielectric constant (low-k) media can reduce the parasitic capacitance introduced by interconnection, but its application also brings many other problems, such as integration problems, reliability problems, etc., and the dielectric constant of low-k materials is also will reach the limit around 1.5

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