Unlock instant, AI-driven research and patent intelligence for your innovation.

A method of fabricating a conductive channel

A conductive channel and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., to achieve the effect of improving mobility and increasing stress

Active Publication Date: 2017-03-29
SEMICON MFG INT (SHANGHAI) CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, how to improve the performance of MOS devices has always been a technical difficulty

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method of fabricating a conductive channel
  • A method of fabricating a conductive channel
  • A method of fabricating a conductive channel

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment 1

[0027] Combine Figure 2a~2g Description as figure 2 The illustrated specific embodiment 1 of the present invention uses the manufacturing process flow of the conductive channel of the MOS device, and the specific steps are as follows:

[0028] Step 21, Figure 2a It is a schematic diagram of the cross-sectional structure of the conductive channel fabrication step 21 of the MOS device of the present invention, such as Figure 2a As shown, a polysilicon layer is deposited on the wafer device surface of the silicon substrate 200, and the polysilicon layer is etched after the first photolithography to form a dummy gate 201.

[0029] In this step, a p-type (or n-type) silicon substrate 200 is provided, in which an STI structure (not shown in the figure) and an active area have been fabricated in the silicon substrate 200, and a MOS is subsequently fabricated above the active area For the device structure, the steps of depositing a polysilicon layer on the device surface of the silicon ...

specific Embodiment 2

[0047] Combine Figure 3a~3g Illustrate the invention as image 3 The specific steps of making the FinFET conductive channel are as follows:

[0048] Step 31, Figure 3a It is a schematic diagram of the cross-sectional structure of the FinnFET conductive channel fabrication step 31 along the length of the fin of the present invention, such as Figure 3a As shown, a fin 301 is formed on the surface of the semiconductor substrate 300.

[0049] In this step, the semiconductor substrate 300 provided is bulk silicon or silicon-on-insulator SOI; the fins 301 are long strips, and the industry generally adopts first to deposit a silicon Si layer on the wafer device surface of the semiconductor substrate 300, and then dry it after photolithography. The method of etching the silicon layer forms the fin 301. Among them, photolithography refers to: coating photoresist on the Si layer, patterning the photoresist to form a photolithography pattern (not shown in the figure) through exposure and d...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
heightaaaaaaaaaa
Login to View More

Abstract

The application discloses a method for producing a conductive channel. A [sigma]-type conductive channel extended to a source electrode and a drain electrode is formed on a semiconductor substrate. On one hand, silicon germanide or silicon carbide grows in the [sigma]-type conductive channel multistep epitaxial in a multistep epitaxial manner. On the other hand, the dosage concentration of non-silicon element on the edge of the [sigma]-type conductive channel is less than that on the center of the [sigma]-type conductive channel. Thus, by means of gradually-varied dosage concentration of non-silicon element, lattice mismatch at interfaces between the source and drain electrodes and the conductive channel is decreased to form heterojunctions, stress in the conductive channel is increased, and migration rates of charge carriers of the source and drain electrodes are increased.

Description

Technical field [0001] The invention relates to a manufacturing technology of a semiconductor device, in particular to a method for manufacturing a conductive channel. Background technique [0002] At present, the semiconductor manufacturing industry mainly grows devices on the wafer device surface of a silicon substrate, for example, Metal-Oxide Semiconductor Field Effect Transistor (MOS). The MOS device structure includes active regions, Source, drain and gate, wherein the active region is located in the semiconductor silicon substrate, the gate is located above the active region, and ion implantation is performed in the active regions on both sides of the gate to form the source And the drain, there is a conductive channel under the gate, and there is a gate dielectric layer between the gate and the conductive channel, such as figure 1 Shown. According to different types of ion implantation, hole type metal oxide semiconductor field effect transistors (PMOS) and electronic ty...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/66568
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP