Drive power amplifier with adjustable gain of 0.1-3GHz CMOS

Abstract

The invention discloses a drive power amplifier with the adjustable gain of a 0.1-3GHz CMOS. The drive power amplifier comprises an input match circuit, an ultra-wideband drive stage amplifying circuit, a gain-adjustable amplifying circuit, an ultra-wideband power amplifying circuit and an output blocking circuit. A first ultra-wideband drive stage is used for achieving preceding-stage gain and ensuring ultra-wideband input match of the whole circuit. A gain control circuit is used for controlling power gain of wideband radio frequency signals and the good inter-ultra-wideband matching property. A third ultra-wideband drive power stage is used for ensuring large power output of the whole circuit and the good wideband output matching property. A three-stage stacking structure is combined with a compensation capacitance circuit, and the area of a chip is small. In the whole circuit, parameters of an adopted component can be determined according to indexes of items such as the whole circuit gain, the wideband and the output power, and therefore the adjustable gain, the high-linearity and the high drive power within the 0.1-3GHz can be achieved.

Description

technical field [0001] The invention relates to the field of complementary metal-oxide-semiconductor (CMOS) radio frequency power amplifiers and integrated circuits, in particular to an ultra-wideband CMOS gain-adjustable drive power amplifier covering the application of industry-specific network frequency bands. Background technique [0002] The rapid development of wireless communication markets such as mobile phones, cordless phones, radio frequency tags (RFID), and wireless local area networks (WLAN) has continuously promoted the development of RF front-end transceivers in the direction of high integration, low power consumption, compact structure, and low price. More and more single-chip radio frequency transceiver communication systems are designed and implemented using cheap and relatively mature and reliable CMOS technology, which requires more and more communication system sub-modules to be designed with CMOS technology while ensuring high performance, so that A hig...

AI Technical Summary

Problems solved by technology

However, the traditional single-stage stacking structure based on CMOS technology has the following problems: 1) low power gain 2) very difficult to match ultra-wideband input 3) serious loss of high-frequency gain

[0010] 1. The chip area of

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