Bottom gate thin film transistor and manufacturing method thereof
A technology of thin film transistors and manufacturing methods, applied in the direction of transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of occupation, large space, unfavorable wiring and aperture ratio, etc., to reduce the ratio, increase the aperture ratio, and wiring The effect of flexibility
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Embodiment 1
[0029] This embodiment provides a method for manufacturing a polysilicon film with a bridge grain (BG) structure, including:
[0030] 1), as attached Figure 2a As shown, a layer of low temperature oxide (LTO) with a thickness of 600nm is deposited on the glass substrate 101 as the barrier layer 201, and then the barrier layer 201 is etched as Figure 2a The rectangular concave-convex structure shown, wherein the width of the groove is 600nm, the depth is 500nm, and the width of the convex teeth is 400nm;
[0031] 2), forming a layer of polysilicon layer 301 with a thickness of 50 nm on the barrier layer 201, the polysilicon layer 301 evenly covers the top of the protruding teeth of the barrier layer 201 and the side walls and bottom of the groove;
[0032] 3), the polysilicon layer 301 is ion-implanted, and the direction of ion implantation is perpendicular to the glass substrate, so that the polysilicon layer 301 at the top of the protruding teeth and the bottom of the groo...
Embodiment 2
[0035] This embodiment provides a method for manufacturing a thin film transistor, including:
[0036] 1), using the method provided in the above-mentioned embodiment 1 to prepare the polysilicon layer 301 with BG lines;
[0037] 2), such as Figure 2b As shown, the polysilicon layer 301 is etched into isolated silicon islands by mask photolithography according to the designed layout;
[0038] 3), using LPCVD (low pressure chemical vapor deposition) to directly deposit a layer of LTO gate insulating layer 401 with a thickness of 80 nm on the polysilicon layer 301;
[0039] 4) Deposit Al / Si-1% alloy on the gate insulating layer 401 as the gate layer, the thickness of the gate layer is 500nm, and the photolithographic gate layer becomes the gate electrode 501, so that the gate electrode 501 covers the unevenness of the polysilicon layer region, the uncovered and doped regions on both sides of the gate are used as source and drain regions;
[0040] 5), using PECVD (Plasma Enhanc...
Embodiment 3
[0045] This embodiment provides a method for manufacturing a thin film transistor, including:
[0046] 1), as attached image 3 As shown, an Al / Si-1% alloy is deposited on a glass substrate 101 as a gate layer, and the thickness of the gate layer is 500 nm, and then the gate layer 201 is etched as Figure 2a As shown in the concave-convex structure, a gate electrode 501 with a concave-convex structure is formed, wherein the width of the groove is 600nm, the depth is 500nm, and the width of the convex teeth is 400nm;
[0047] 2) On the gate electrode 501, an LTO gate insulating layer 401 with a thickness of 80nm is formed to cover the top of the protruding teeth on the gate and the side walls and bottom of the groove, and cover the end faces at both ends of the gate and the two sides of the gate. side glass substrate;
[0048] 3), depositing a polysilicon layer 301 with a thickness of 50 nm on the gate insulating layer 401, the polysilicon layer 301 covers the top of the prot...
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