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Magnetic bit cell double voltage writing method

A bit cell, dual-voltage technology, applied in the field of new non-volatile random access memory, can solve the problem of wasteful writing power consumption, achieve the effect of reducing power consumption and maximizing utilization

Active Publication Date: 2014-05-14
致真存储(北京)科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] 1. Purpose: Based on the fact that the actual voltage required for the two write operations of the magnetic tunnel junction is less than Vdd, and the asymmetric characteristics of the voltage and current required for the two write operations, the magnetic tunnel junction write mentioned in the above background In order to solve the problem of unnecessary waste of input power consumption, the present invention provides a dual-voltage writing method for magnetic bit cells, which is a method for writing "0" and writing "1" operations using dual voltages, thereby reducing the number of write operations. operating power consumption, maximizing utilization of magnetic tunnel junction write power consumption

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Embodiment Construction

[0032] See figure 1 — Figure 8 , random access memory usually organizes its storage bit cells in an array. Such as Figure 8 According to the disclosure, the memory array of the magnetic random access memory organizes a plurality of bit cells together in the manner of rows and columns. All bit cells in each row share a word line, and each independent bit cell in a row has its own bit line and source line; all bit cells in each column share a bit line and a source line, and each independent bit cell in a column The bit cells have their own word lines. Figure 8 The ellipsis in indicates that there can be multiple bit cells in each column, and similarly, there can be multiple bit cells in each row.

[0033] When addressing and accessing a specific bit cell in the memory array of the magnetic random access memory, it is necessary to apply a high voltage to the word line of the row where the accessed bit cell is located to turn on the NMOS transistor in the bit cell, and the ...

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Abstract

A magnetic bit cell double voltage writing method comprises the following four steps that step 1, an address of a line to which a bit cell to be written belongs needs to be found out to determine the location of the line to which the bit cell to be written belongs in a storage array; step 2, according to a requirement of writing '0' or '1', a writing circuit is associated with a corresponding writing voltage, so that the voltage and current which are required by the operation of writing '0' or '1' are prepared; step 3, an address of a row to which the bit cell to be written belongs needs to be found out to determine the location of the row to which the bit cell to be written belongs in the storage array; the step 3 works together with the step 1, so that a specific location of the bit cell to be written in the storage array is determined; step 4, through the step 1, the step 2 and the step 3, a current path from an associated writing voltage to an earth wire Gnd through the bit cell is formed; according to the requirement of writing '0' or '1', the currents flow from a bit line of the bit cell to a source line of the bit cell or from the source line of the bit cell to the bit line of the bit cell respectively, and the operation of writing '0' or '1' is completed.

Description

technical field [0001] The invention relates to a magnetic random access memory, in particular to a magnetic bit cell dual-voltage writing method used in the magnetic random access memory with planar magnetic anisotropy and perpendicular magnetic anisotropy. The present invention is also applicable to write operations in any non-volatile memory or non-volatile logic circuit based on an asymmetric write mechanism. The invention belongs to the technical field of novel non-volatile random access memory in semiconductor memory. Background technique [0002] Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is generally considered to be a A storage technology that replaces the existing volatile static random access memory (SRAM) and dynamic random access memory (DRAM). [0003] The core storage element of spin-transfer torque magnetoresistive random access memory is the magnetic tunnel junction (MTJ). It is mainly a three-layer stack structure, a free layer...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 郭玮赵巍胜
Owner 致真存储(北京)科技有限公司