Method for reducing ohmic contact resistance of HEMT device
A technology of ohmic contact and devices, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unsatisfactory surface morphology and edge uniformity, and GaN material damage
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0038] In this embodiment, the AlGaN / GaN HEMT device material is taken as an example, and the embodiments of the present invention are described in detail with reference to the accompanying drawings:
[0039] figure 1 It is a schematic diagram of the structure of AlGaN / GaN HEMT device materials after step 1); 150nm silicon dioxide (SiO 2 ),Such as figure 2 Shown; use reactive ion etching equipment (RIE) to etch SiO in the source and drain ohmic regions of HEMT devices 2 Layer to the upper surface of the AlGaN barrier layer, such as image 3 As shown, the above steps can be implemented by existing technology.
[0040] The invention of the present invention lies in the use of inductively coupled plasma etching equipment (ICP) to etch the source and drain ohmic regions of the HEMT device after the GaN is etched and before the secondary epitaxial growth of n-type heavily doped GaN, the thermal rapid annealing equipment is used to remove the above materials Low-temperature annealing tr...
Embodiment 2
[0044] In this embodiment, the InAlN / GaN HEMT device material is taken as an example to illustrate the implementation of the present invention in detail:
[0045] Grow 200nm silicon dioxide on the surface of InAlN / GaN material (SiO 2 ) Layer; use reactive ion etching equipment (RIE) to etch SiO in the source and drain ohmic regions 2 Layer to the upper surface of the InAlN barrier layer; use inductively coupled plasma etching equipment (ICP) to etch the GaN material in the source and drain ohmic regions of the HEMT device, and etch below the InAlN / GaN heterojunction interface (the etching depth is about 50nm ), and then use a high-temperature annealing furnace to anneal the above devices in a pure nitrogen atmosphere (other protective gases can also be used) or a vacuum atmosphere. The annealing temperature is 300°C and the time is 3 minutes; the MOCVD equipment is used to process the above devices The source and drain ohmic region of the second epitaxy 60nm n-type heavily doped G...
Embodiment 3
[0047] In this embodiment, the InAlN / GaN HEMT device material is taken as an example to illustrate the implementation of the present invention in detail. The focus of this embodiment is on the adjustment of process parameters:
[0048] Grow 200nm silicon dioxide on the surface of InAlN / GaN material (SiO 2 ) Layer; use reactive ion etching equipment (RIE) to etch SiO in the source and drain ohmic regions 2 Layer to the upper surface of the InAlN barrier layer; use inductively coupled plasma etching equipment (ICP) to etch the GaN material in the source and drain ohmic regions of the HEMT device, and etch below the InAlN / GaN heterojunction interface (the etching depth is about 40nm ), and then use a high-temperature annealing furnace to anneal the above-mentioned devices in a pure nitrogen atmosphere (other protective gases can also be used) or a vacuum atmosphere. The annealing temperature is 800°C and the time is 0.5 minutes; the MOCVD equipment is used to process the above-mention...
PUM
Property | Measurement | Unit |
---|---|---|
thickness | aaaaa | aaaaa |
thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com