Reballing method for inverted packaging of semiconductor integrated circuit or discrete device

A technology of integrated circuits and discrete devices, which is applied in the field of bump packaging of semiconductor integrated circuits or discrete devices, which can solve the problems of poor heat dissipation and large parasitic effects, and achieve simple process, small parasitic parameters and low curing temperature Effect

Inactive Publication Date: 2014-10-01
TIANSHUI TIANGUANG SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to solve the problems of large parasitic effect and poor heat dissipation function of the traditional packaging method, the present invention provides a ball plantin

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0015] Example 1

[0016] 1) Bump bottom metallization

[0017] The three-layer metals of titanium, nickel and silver are sputtered or evaporated in sequence on the chip completed by pressure point lithography. The thickness of titanium, nickel and silver is 1800 mm, respectively. , 3600 , 4500 , the composite metal layer is used to connect the wiring metal and solder balls in the chip, and then the composite metal layer outside the pressure point on the chip is etched by photolithography, and the composite metal layer on the pressure point is retained.

[0018] 2) Apply a layer of tin flux to the chip with a thickness of 48 microns.

[0019] 3) Place a solder ball with a diameter of 290 microns on the above-mentioned composite metal layer of the chip coated with tin flux, heat the chip to 220°C, the solder ball is welded to the composite metal on the chip through the flux, and the metal wire inside the chip is welded. The composite metal layer on the pressure point is ...

Example Embodiment

[0020] Example 2

[0021] 1) Bump bottom metallization

[0022] The three-layer metals of titanium, nickel and silver are sputtered or evaporated in sequence on the chip completed by point lithography. The thicknesses of titanium, nickel and silver are 1860 mm, respectively. , 3980 , 5340 . The composite metal layer is used to connect the wiring metal and the solder balls in the chip, and then the composite metal layer outside the pressure point on the chip is etched by photolithography, and the composite metal layer on the pressure point is retained.

[0023] 2) Apply a layer of tin flux to the chip with a thickness of 56 microns.

[0024] 3) Place a tin ball with a diameter of 300 microns on the above-mentioned composite metal layer of the chip coated with tin flux, heat the chip to 240 ° C, and weld the tin ball with the composite metal on the chip through the flux, and the metal wire inside the chip The composite metal layer on the pressure point is bonded t...

Example Embodiment

[0025] Example 3

[0026] 1) Bump bottom metallization

[0027] The three-layer metals of titanium, nickel and silver are sputtered or evaporated in sequence on the chip completed by point lithography. The thicknesses of titanium, nickel and silver are 2200 mm, respectively. , 4400 , 5500 . The composite metal layer is used to connect the wiring metal and the solder balls in the chip, and then the composite metal layer outside the pressure point on the chip is etched by photolithography, and the composite metal layer on the pressure point is retained.

[0028] 2) Apply a layer of tin flux to the chip with a thickness of 50 microns.

[0029] 3) Place a solder ball with a diameter of 295 microns on the above-mentioned composite metal layer of the chip coated with tin flux, heat the chip to 230 ° C, and weld the solder ball to the composite metal on the chip through the flux, and the metal wire inside the chip The composite metal layer on the pressure point is bonded to t...

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PUM

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Abstract

The invention provides a reballing method for inverted packaging of a semiconductor integrated circuit or a discrete device. The method includes the steps that (1) metallization is conducted on the bottom of a salient point; (2) a chip is coated with a layer of tin scaling powder with the thickness being 50 micrometers; (3) a salient point welding ball is manufactured on the chip. According to the method, after the chip is manufactured, few processes are added, and a semiconductor device which is small in size, small in parasitic parameter, excellent in performance and capable of being directly arranged on a PCB in an inverted mode is manufactured. According to the method, a traditional packaging technology is greatly simplified, the production cost is reduced, and the production efficiency is improved. The added processes have the advantages of being simple in technology, low in curing temperature (about 230 DEG C) and capable of conducting batch processing conveniently.

Description

technical field [0001] This patent belongs to the packaging and manufacturing of semiconductor integrated circuits or discrete devices, specifically a ball planting method for upside-down packaging of semiconductor integrated circuits or discrete devices. Background technique [0002] As people's requirements for miniaturization and high performance of electronic products are getting higher and higher, electronic components tend to be smaller in size, lighter in weight, and require higher reliability at the same time. The packaging of components has developed from traditional DIP and other forms to miniaturization. In recent years, advanced packaging forms such as SOT, SOP, QFP, QFN, and BGA have emerged, and have been widely used in computers, automotive electronics, and consumer electronics. Due to the rapid development of portable devices, components are required to be smaller in size, with low parasitic effects and good heat dissipation. Advanced packaging forms such as...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L21/4853
Inventor 徐谦刚王永功刘惠林韩国栋杨虹薛建国
Owner TIANSHUI TIANGUANG SEMICON
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