Manufacturing method for semiconductor device

Abstract

The invention provides a manufacturing method for a semiconductor device. After a source-drain region groove is formed by a conventional etching process, the formed source-drain region groove is processed by using an in-situ etching process, thereby repairing the damage of a substrate lattice due to the conventional etching; moreover, the side wall, adjacent to a channel region, of the source-drain region groove forms a {111} and / or {113} surface and extends towards the channel region, thereby providing the greater stress for the channel region beneficially. Meanwhile, because the in-situ etching process and the epitaxy process are carried out simultaneously in an expitaxy machine platform, waiting time between the formation process of the source-drain region groove and the epitaxy process is substantially reduced, thereby inhibiting formation of an interface oxidation layer and absorption of carbon in air by the inner wall of the groove, reducing the subsequent epitaxial defect source, and avoiding the influence on doped element distribution in a substrate due to the high temperature process used for eliminating the natural oxidation layer and the carbon according to the conventional process.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing methods, in particular to a semiconductor device manufacturing method for epitaxially forming source and drain regions of transistors. Background technique [0002] Since the first transistor was invented, integrated circuits have been advancing at breakneck speed, fueled by a series of innovative efforts. After entering the 90nm node, strained silicon technology has become a basic technology to improve the performance of MOSFET devices by suppressing the short channel effect and improving carrier mobility. Related to it, stress technologies such as STI (Shallow Trench Isolation), SPT (Side Wall Patterning Technology), source and drain silicon germanium embedding, metal gate stress, etch stop layer (CESL) have been proposed and integrated. For PMOS devices, the source and drain using SiGe is gradually adopted by mainstream CMOS manufacturers after entering the 90nm node. Specifi...

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Problems solved by technology

[0003] However, in the existing process, after the source and drain grooves are formed by etching, there are more damages on the inner surface of the grooves, which will have a negative impact on the subsequent epitaxial process, which will lead to the introduction of gravitational failure.

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