A Read Amplifier Circuit with Process Deviation Tolerance and Read Disturb Elimination

Abstract

The invention provides a process deviation tolerating and reading interference eliminating reading amplifying circuit, which consists of a current conveyor, a load circuit, a charge transferring voltage amplifier and a dynamic latch voltage comparator, wherein one input end Y of the current conveyor is connected with an STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) data unit array to be read and an STT-MRAM reference unit array to be read through a bit line selector; the other input end X of the current conveyor is connected with an external bias voltage V<bias>; the output end Z of the current conveyor is simultaneously connected with the load circuit and the input end of the charge transferring voltage amplifier; the other end of the load circuit is connected with a power supply voltage source Vdd; the output end of the charge transferring voltage amplifier is connected with the input end of the dynamic latch voltage comparator; and the output end of the dynamic latch voltage comparator outputs final read binary data signals. The reading amplifying circuit provided by the invention has the advantages that the problem of conflict between the reading interference and the reading judging allowance in the STT-MRAM technology is solved, and the reading reliability of an STT-MRAM is improved.

Description

technical field [0001] The invention provides a read amplifier circuit with process deviation tolerance and read interference elimination, which belongs to the technical field of non-volatile STT-MRAM memory. Background technique [0002] In recent years, the new spin transfer torque magnetic random access memory STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) technology has been continuously developed, has become more and more mature, and has gradually begun to be used in actual industrial production. The basic storage unit of STT-MAM is mainly composed of a magnetic tunnel junction MTJ (Magnetic Tunneling Junction) and an N-type metal oxide semiconductor NMOS (N-Metal-Oxide-Semiconductor) transistor. Among them, MTJ is used for data storage, while NMOS transistor is used for access control of memory cells. MTJ is mainly composed of three layers of film, such as figure 1 As shown, that is, the upper and lower layers are ferromagnetic layers, and the middle i...

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Problems solved by technology

[0003] At present, the large-scale production and popularization of STT-MRAM is facing serious read reliability problems: (1) Due to the limitations of materials and manufacturing processes, the TMR value that can be obtained at room temperature is relatively small, so the available read judgment margin is relatively small. The amount is relatively small, when the read decision margin cannot overcome the device mismatch (Device Mismatch) or input offset (Input Offset) of the read circuit itself, a read error occurs; (2) The continuous shrinking of the process size leads to serious Process deviation, resulting in serious device mismatch (including the STT-MRAM memory cell itself and peripheral circuits, etc.), these factors further reduce the read decision margin of STT-MRAM, while increasing the input offset of the read circuit, affecting Read reliability performance; (3) In order to increase the read decision margin and improve the read reliability, it is necessary to provide a larger external read current, but due to the existence of the STT effect, an excessively large external current may affect the STT-MRAM The data stored in the data unit or reference unit is rewritten, causing read disturbance. It can be seen that there is a contradiction between read disturbance and read decision margin.

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