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Adaptive and asynchronous routing network on 2D-Torus chip and design method thereof

A 2d-torus, network-on-a-chip technology, applied in data exchange networks, digital transmission systems, electrical components, etc., can solve problems such as reducing data transmission efficiency, dynamically adjusting routing directions, and unable to respond to congestion status in real time.

Active Publication Date: 2015-01-28
NORTHEASTERN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this type of algorithm is passive and blind. It can only distribute and transmit data packets in advance, and cannot dynamically adjust the routing direction according to the congestion status in real time.
Therefore, when the network is congested, routing resources may be wasted, and the efficiency of data transmission will be reduced, which will eventually lead to a rapid decline in routing performance.

Method used

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  • Adaptive and asynchronous routing network on 2D-Torus chip and design method thereof
  • Adaptive and asynchronous routing network on 2D-Torus chip and design method thereof
  • Adaptive and asynchronous routing network on 2D-Torus chip and design method thereof

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Embodiment Construction

[0057] The specific implementation of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0058] The route-adaptive asynchronous 2D-Torus network-on-chip of this embodiment adopts a 4×4 structure, such as figure 1 As shown, it includes: 16 asynchronous routing nodes and 16 IP cores, of which 16 asynchronous routing nodes, according to the 2D-Torus topology structure, adopts the asynchronous handshake communication mechanism to form a 4×4 asynchronous 2D-Torus network on chip. One IP core is mounted on each asynchronous routing node; the asynchronous routing node is used to send data from the corresponding output port to the adjacent node according to the information carried in the data, until the current asynchronous routing node is the destination address asynchronous routing node;

[0059] The asynchronous routing node in this embodiment, such as figure 2 As shown, the asynchronous routing node has five ports including ...

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Abstract

The invention discloses an adaptive and asynchronous routing network on a 2D-Torus chip and a design method thereof, wherein multiple asynchronous routing nodes are used to create the network on the chip according to a 2D-Torus topological structure and an asynchronous handshake communication mechanism; each asynchronous routing node respectively includes east, west, south, north and local ports, each port includes an input end, a data receiving module, a data decoding module, a routing calculation module, a crossbar switch module, a data mediation module, a data encoding module, a data transmitting module and an output end; the method comprises the following steps of: designing interface behavior of each port included in the asynchronous routing node, and describing the data flow direction in the asynchronous routing node; designing a data structure of transmission data from the asynchronous network on the chip; designing the module in the port by an asynchronous finite-state machine method; achieving hardware programming to each module; creating the asynchronous routing node; creating the N*N asynchronous network on the 2D-Torus chip.

Description

technical field [0001] The invention belongs to the field of asynchronous circuit design, and in particular relates to a route-adaptive asynchronous 2D-Torus (two-dimensional ring) on-chip network and a design method thereof. Background technique [0002] With the rapid development of integrated circuit technology, the scale of the system is getting larger and larger, and the clock frequency is getting higher and higher. Problems with traditional bus clocking and power consumption are becoming more and more difficult to solve. A network on chip (Network on Chip, NoC) can solve these problems very well, and has gradually become a standard communication architecture for multi-core on a chip. At present, most networks on a chip adopt a synchronous communication mechanism, and the communication between network nodes is driven by a single clock. Only a small number of on-chip networks use asynchronous communication mechanisms, and the communication between network nodes is cont...

Claims

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Application Information

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IPC IPC(8): H04L12/741H04L12/771H04L12/865H04L45/74H04L45/60H04L47/6275
Inventor 李贞妮李晶皎方志强
Owner NORTHEASTERN UNIV