Polishing method of TSV

Abstract

The invention discloses a through-silicon via polishing method which comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate is provided with a through-silicon via and covered with a copper layer which fills the through-silicon via; the copper layer is polished for the first time; and the copper layer is polished for the second time to form a copper wire layer, wherein the down force of the second polishing is smaller than the down force of the first polishing. According to the through-silicon via polishing method of the invention, the copper layer is polished step by step and the down force of the second polishing is decreased, so that the rate of copper grinding can be reduced, the dent defect in the through-silicon via can be reduced or eliminated, and the electrical performance of the device can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a polishing method for through-silicon holes. Background technique [0002] With the development of people's requirements for electronic products in the direction of miniaturization, multi-function, and environmental protection, people strive to make electronic systems smaller and smaller, with higher integration and more functions. As a result, many new technologies, new materials and new designs have emerged. For example, stacked chip packaging technology and system-in-package technology are typical representatives of these technologies. The former is referred to as 3D packaging technology, which refers to the packaging technology of stacking two or more chips in the same package in the vertical direction without changing the size of the package. [0003] Among many 3D packaging technologies, Through-Silicon Via (TSV) technology is the hotspot of current research. TSV t...

AI Technical Summary

Problems solved by technology

However, due to the large aspect ratio of TSV, after the copper electroplating process, a filling ring will appear on the copper surface above the through hole, such as figure 1 As shown, the semiconductor substrate 100 has a TSV 110, the semiconductor substrate 100 is covered with a copper layer 200, the copper layer 200 fills the TSV 110, and the copper surface above the copper layer 200 will be having a filled ring 210, figure 2 It is a scanned electronic picture of the filled ring 210, after the CMP process, the position of the filled ring will appear as follows image 3 The dent defect shown, which affects the electrical performance of the device

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