Sonos non-volatile memory and manufacturing method thereof

Abstract

The invention discloses a SONOS non-volatile memory. The gates of the SONOS memory transistor and the selection transistor of the unit structure are overlapping two-layer structures isolated by an insulating layer. The first side of the selection transistor is formed with a first insulating dielectric side. wall, the tunnel injection region and the ONO layer of the SONOS memory transistor are all self-aligned with the first insulating dielectric side wall; the entire unit structure only includes two source and drain regions, which do not exist between the gates of the SONOS memory transistor and the selection transistor. Source and drain areas. The invention also discloses a manufacturing method of SONOS non-volatile memory. The present invention directly eliminates a source-drain region between the two transistor gates, can greatly reduce the area of ​​the memory unit, and does not require additional photolithography steps.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to one. Background technique [0002] SONOS non-volatile memory is widely used in advanced flash memory and electrically erasable memory products. At present, the commonly used memory cell structure consists of a complete SONOS memory transistor and a complete select transistor to form a 2-transistor structure (2T structure), each transistor has a complete source, drain and gate, and the two transistors share a layer polysilicon. like figure 1 Shown is the cell structure diagram of the existing SONOS non-volatile memory; the cell structure of the existing SONOS non-volatile memory includes a SONOS memory transistor and a selection transistor, the cell structure is formed in the P well 102, the P Well 102 is formed in deep N-well 101 of silicon substrate 100 . [0003] The gate structure of the SONOS memory transistor includes an ONO layer 104 and...

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Problems solved by technology

This further limits the shrinkage of the memory cell structure

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