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Electrical performance test structure and manufacturing method and electrical performance testing process thereof

A technology of electrical testing and process, applied in the field of semiconductor device testing, can solve the problems of difficult to distinguish the test structure, wide bandwidth of the probe tip, and difficult alignment

Inactive Publication Date: 2015-04-22
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1) It is difficult to distinguish the pattern of the test structure (test structure) under the optical microscope (optical system), and because the size of the polysilicon gate and the tip of the probe are small, and the broadband of the probe tip relative to the polysilicon gate is relatively large Large, which makes it very difficult to align during testing
[0006] 2) It is easy to cause sample damage (sample damage)
[0008] 4) P-type doped wafers can only be used in the measurement process of the capacitance of NMOS devices (with P substrates)

Method used

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  • Electrical performance test structure and manufacturing method and electrical performance testing process thereof
  • Electrical performance test structure and manufacturing method and electrical performance testing process thereof
  • Electrical performance test structure and manufacturing method and electrical performance testing process thereof

Examples

Experimental program
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Embodiment 1

[0047] figure 1 is a top view of the electrical test structure in the embodiment of the present application, figure 2 It is a cross-sectional view of the electrical test structure in the embodiment of the present application; as Figure 1~2 As shown, the electrical test structure in this embodiment includes:

[0048] A substrate 1, a first shallow trench isolation structure (STI) 11, a second shallow trench isolation structure 12 and a third shallow trench isolation structure 13 are arranged on the substrate 1, and the substrate 1 is also provided with The gate region 4, and the first test region 5 and the second test region 6 located on both sides of the gate region 4; wherein, the above-mentioned first shallow trench isolation structure 11 spans the first test region 5 and the gate region 4 (That is, a part of the first shallow trench isolation structure 11 is located in the above-mentioned first test area 5, and the remaining part is located in the gate area 4, such as f...

Embodiment 2

[0057] image 3 It is a schematic flow diagram of the method for preparing the electrical test structure in the embodiment of the present application; as Figure 1~3 As shown, a method for preparing an electrical test structure can be applied to prepare the electrical test structure in Example 1, the method comprising:

[0058] Firstly, a substrate 1 is provided, and several shallow trench isolation structures are arranged in the substrate 1; preferably, the first shallow trench isolation structure 11 and the second shallow trench isolation structure can be arranged in the substrate 1. 12 and the third shallow trench isolation structure 13, and the above-mentioned second shallow trench isolation structure 12 is located between the first shallow trench isolation structure 11 and the third shallow trench isolation structure 13, and in the second shallow trench isolation structure A pickup region (pickup) can be formed on the substrate between the isolation structure 12 and the ...

Embodiment 3

[0069] On the basis of embodiment one and embodiment two, based on the above-mentioned electrical test structure, such as Figure 1~3 As shown, when conducting an electrical test on the gate oxide layer 2, two probes can be used to electrically connect the above-mentioned first micro pad 51 and the second micro pad 62 respectively, and then the electrical test process of the gate oxide layer 2 can be performed. .

[0070] The electrical testing process in this embodiment is carried out on the basis of Embodiment 1 and Embodiment 2. In order to make the description concise and clear, it will not be repeated here, but the technical solution in this embodiment includes Embodiment 1 And all the technical characteristics described in the second embodiment.

[0071] In addition, since the above-mentioned first micro-pad 51 is directly connected to the gate structure located in the gate region 4, and the second micro-pad 62 is directly defined on the pick-up area of ​​the substrate ...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an electrical performance test structure and a manufacturing method and an electrical performance testing process of the electrical performance test structure. The electrical performance testing process can be applied to testing of electrical performance of a gate oxide before manufacturing of an interlayer dielectric layer and before a back-end process. Namely, a micro pad connected with the gate oxide and a substrate is arranged on the electrical performance test structure with a grid electrode, the testing process difficulty is greatly lowered, and on the premise of not damaging a wafer substrate, the electrical performance test on the gate oxide of an NMOS component and a PMOS component is achieved, so that test samples are prevented from being damaged, the test efficiency is greatly improved, and the process cost is effectively lowered.

Description

technical field [0001] The invention relates to the technical field of semiconductor device testing, in particular to an electrical testing structure, a preparation method thereof, and an electrical testing process. Background technique [0002] In the manufacturing process of semiconductor devices, according to some special needs, before the formation of the interlayer dielectric layer (Inter Layer Dielectrics, ILD for short), sometimes it is necessary to measure the prepared test pad (probing pad) The electrical properties of the gate oxide. [0003] Traditional methods for measuring the gate oxide layer mainly include nanoprobe measurement method (Nano prober) and manual measurement method (Manual prober); however, the gate oxide layer of the prepared semiconductor device is During electrical measurement, the wafer needs to be broken when preparing samples, and the test time for preparing samples and nanoprobes is very long (long time for sample preparation), which takes...

Claims

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Application Information

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IPC IPC(8): H01L23/544H01L21/66
Inventor 郭强龚斌
Owner WUHAN XINXIN SEMICON MFG CO LTD
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