A multi-port memory access controller for multi-processor and its control method

Abstract

The invention relates to a multiport access and storage controller for a multiprocessor. The multiport access and storage controller comprises an instruction channel, wherein an input terminal of the instruction channel is connected with an output terminal of a peripheral DMA (Direct Memory Access) channel of the multiprocessor and an output terminal of a kernel DMA channel of the multiprocessor respectively, an output terminal of the instruction channel is connected with an input terminal of an arbitration module, an output terminal of the arbitration module is connected with an input terminal of a memory array, an output terminal of the memory array is connected with an input terminal of a data channel, and an output terminal of the data channel is connected with an input terminal of the peripheral DMA channel of the multiprocessor and the input terminal of the kernel DMA channel of the multiprocessor respectively. The invention further discloses a control method for the multiport access and storage controller for the multiprocessor. According to the multiport access and storage controller and the control method, an effective response mechanism is provided for concurrent requests of multiple DMA channels, and the characteristics, namely the real time of request response and the full utilization of memory bandwidth, are all taken into account, so that the throughput rate of access and storage data can be increased, and wait time resulting from address conflict is reduced.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a multi-port memory access controller for multi-processors and a control method thereof. Background technique [0002] The invention of the multi-port memory access controller is to solve the storage and exchange work of a large amount of data in the multi-processor core and integrated high-speed peripheral hardware on-chip. For the memory array composed of SRAM, it is necessary to take advantage of the simple and easy-to-operate characteristics of its read and write ports, and also take into account the rationality of the multi-channel concurrent request arbitration mechanism to give full play to the maximum data bandwidth. [0003] In the past, the multi-port memory access controller continued to use the characteristics of request and data serial input and serial output. For the memory composed of single-port SRAM, when multiple requests take effect at the sam...

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Problems solved by technology

[0003] In the past, the multi-port memory access controller continued to use the characteristics of request and data serial input and serial output. For the memory composed of single-port SRAM, when multiple requests take effect at the same time and conflict, they will often select one of them to enter the storage unit according to the priority. The remaining requests will wait, reducing the throughput rate of fetching data

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