Semi-floating gate memory, its manufacturing method and half-floating gate memory array

Abstract

The invention discloses a semi-floating gate memory, which comprises at least one U-shaped groove formed in a semiconductor substrate, one buried source region formed in the semiconductor substrate at the bottom of the U-shaped groove, and two buried source regions formed in the semiconductor substrate at the bottom of the U-shaped groove. Drain regions respectively formed in the semiconductor substrate on both sides of the U-shaped groove, a control gate and two floating gates for storing charges formed in the U-shaped groove, the control gate and any one of the floating gates formed in the U-shaped groove The combination of the drain region selects one floating gate, and two gate-controlled pn junction diodes respectively formed in the semiconductor substrate on both sides of the U-shaped groove and connected to the drain region and the floating gate. A half-floating gate memory array, in which the angle between the bit line and the corresponding active area is less than 80 degrees, more half-floating gate memories can be manufactured in the same semiconductor substrate size, and high-density storage can be realized. The invention adopts a self-alignment process to manufacture the half-floating gate memory and the half-floating gate memory array, and the process is simple and easy to control.

Description

technical field [0001] The invention relates to a semiconductor memory, a semiconductor memory array and a manufacturing method thereof, in particular to a half-floating gate memory, a manufacturing method thereof and a half-floating gate memory array, belonging to the technical field of semiconductor memory. Background technique [0002] Semiconductor memories are widely used in various electronic products. Different application areas place different requirements on the structure, performance and density of semiconductor memories. For example, static random access memory (SRAM) has high random access speed and low integration density, while standard dynamic random access memory (DRAM) has high density and medium random access speed. [0003] Chinese patent 201310158971.4 proposes a semi-floating gate memory with a vertical channel, such as figure 1 As shown, it includes a vertical channel region 401 formed in the semiconductor substrate 200 with the first doping type, and...

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Problems solved by technology

[0005] However, the floating gate 205 of the above-mentioned vertical channel semi-floating gate memory can only store one cell, and the contact body 211 of the source region 201 is isolated from the control gate 207 by the gate spacer 208, and leads to the top of the semiconductor substrate 200. , which increases the size of the device and reduces the chip density

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