Transistor forming method

Abstract

The invention provides a transistor forming method. The method includes providing a substrate; forming a false grid structure comprising a false grid on the surface of the substrate; forming a source region and a leak region on the substrate exposed in the false grid structure; forming an interlayer medium layer aligned with the false grid structure on the substrate; removing majority of the false grid of the false grid structure by dry etching; performing first dry washing on the surface of the remained false grid; performing wet washing on the surface of the remained false grid; performing second dry washing on the surface of the remained false grid; removing the remained false grid by wet etching, and forming an opening corresponding to the false grid in the shape; forming a grid medium layer and a metal grid electrode in the opening. By means of the first dry washing, the wet washing and the second dry washing, the contaminant remained on the surface of the false grid is removed after the false grid is formed by dry etching, and the performance of a transistor is optimized.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a method for forming a transistor. Background technique [0002] In the high-K dielectric / metal gate engineering of transistors, after high-temperature annealing for ion activation, dummy gates such as polysilicon gates need to be removed, and then filled with metal gate electrodes to form a high-K dielectric / metal gate structure. [0003] refer to figure 1 and figure 2 , shows a method for forming a transistor in the prior art. Such as figure 1 As shown, the shallow trench isolation region 08 is formed in the substrate 01, the dummy gate structure of the NMOS transistor is formed on the left side of the shallow trench isolation region 08, and the dummy gate structure of the PMOS transistor is formed on the right side, and each dummy gate structure Including a gate dielectric layer 03, a capping layer 06, and a dummy gate 02, the sidewall of the dummy gate structure is ...

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Problems solved by technology

The dummy gate 02 is usually formed of polysilicon. In the prior art, a combination of anisotropic dry etching and wet etching is generally used to remove the dummy gate 02 made of polysilicon. However, in the prior art, ...

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