[0042] Example
[0043] This embodiment provides an organic light emitting display device, such as image 3 As shown, it includes a substrate 110, thin film transistors, capacitors and organic light emitting diodes arranged in the display area 1 of the substrate, and electrode power lines 210 arranged in the non-display area 2 of the substrate 110.
[0044] The substrate 110 is selected from but not limited to a glass substrate or a polymer substrate, and a glass substrate is preferred in this embodiment.
[0045] A buffer layer 120 is directly formed on the substrate 110. The buffer layer is selected from but not limited to a one-layer or multi-layer stack structure formed by silicon oxide and/or silicon nitride, and has a thickness of 40-400 nm. This embodiment Preferably, the silicon oxide layer has a thickness of 230 nm.
[0046] The organic light emitting diode includes a first electrode 161, an organic light emitting layer 162, and a second electrode 163 stacked in sequence. The first electrode 161 is electrically connected to the source electrode 135 or the drain electrode 136 of the thin film transistor, and the second electrode 163 is connected to the electrode power line. 210 Contact electrical connection.
[0047] The first electrode 161 is selected from, but not limited to, one or more stacked layers formed of indium tin oxide (ITO) and/or indium zinc oxide (IZO), with a thickness of 50 to 150 nm, which is preferred in this embodiment The ITO layer has a thickness of 90nm.
[0048] The second electrode 163 is selected from, but not limited to, one or more alloys of calcium, aluminum, magnesium, silver and their alloys, or a stacked layer formed by one or more layers of LiF, with a thickness of 10-100 nm. The preferred embodiment is a magnesium-silver alloy layer with a thickness of 30 nm.
[0049] The organic light-emitting layer 162 is tris (8-hydroxyquinoline) aluminum (Alq 3 ), the thickness is 45nm. As another embodiment of the present invention, the material of the organic light-emitting layer 162 can be selected from any of the prior art organic small molecules or polymer molecular light-emitting substances, which can achieve the purpose of the present invention and belong to the protection scope of the present invention.
[0050] As another embodiment of the present invention, the organic light emitting diode further includes one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. In combination, the materials and thicknesses of the above functional layers are the same as those in the prior art, and will not be repeated in this embodiment.
[0051] The thin film transistor in this embodiment is preferably a top-gate thin film transistor, that is, in the vertical direction, the semiconductor layer 131, the gate layer 133, and the source/drain electrode layer of the thin film transistor are sequentially arranged from bottom to top.
[0052] The semiconductor layer 131 and the gate layer 133 are further provided with a first insulating layer 132 to insulate them from each other; the gate layer 133 and the source/drain electrode layer are also provided with a first insulating layer to insulate them from each other. The second insulating layer 134; the source/drain electrode layer in the source 135 and drain 136 can be interchanged.
[0053] The semiconductor layer 131 is selected from, but not limited to, a polysilicon layer, an amorphous silicon layer or a metal oxide semiconductor layer, and has a thickness of 30-80 nm. In this embodiment, a polysilicon layer is preferably 50 nm in thickness.
[0054] The first insulating layer 132 is selected from, but not limited to, one or more stacked layers formed of silicon oxide, silicon nitride, or aluminum oxide, and has a thickness of 50-150 nm. In this embodiment, a silicon oxide layer is preferably 100 nm in thickness.
[0055] The gate layer 133 is selected from but not limited to one or more stacked layers formed by one or more of molybdenum, tungsten, chromium, aluminum, copper and alloys thereof, and has a thickness of 200-400 nm. This embodiment is preferred The molybdenum layer has a thickness of 300 nm.
[0056] The second insulating layer 134 is selected from, but not limited to, one or more stacked structures formed by silicon oxide and/or silicon nitride, and has a thickness of 200-500 nm. In this embodiment, a silicon nitride layer is preferably 400 nm in thickness.
[0057] The source/drain electrode layer is selected from, but not limited to, one or more stacked structures formed by one or more of titanium, silver, copper, aluminum and alloys thereof, and has a thickness of 300-600 nm. In this embodiment, aluminum is preferred. Layer with a thickness of 400nm.
[0058] The electrode power line 210 and the gate 133 or the source/drain electrode layer of the thin film transistor are formed of the same material in the same layer; in this embodiment, the electrode power line 210 and the source/drain electrode layer are preferably formed in the same layer. The same material is formed. As another embodiment of the present invention, the thin film transistor may also have a bottom gate structure or a double gate structure, both of which can achieve the purpose of the present invention and belong to the protection scope of the present invention.
[0059] The second insulating layer 134 is directly provided with a planarization layer 150 covering the source/drain electrode layer, and the planarization layer 150 extends to the non-display area 2 and covers the edge of the electrode power line 210; The first electrode 161 is directly disposed on the planarization layer 150; the first electrode 161 is connected to the source electrode 135 or the drain electrode 136 through a first through hole disposed on the planarization layer 150 Contact and electrical connection; the auxiliary conductive layer 220 is in contact with the electrode power line 210 through a second through hole provided on the planarization layer 150, and the auxiliary conductive layer 220 extends to cover the second through hole On the side walls.
[0060] The planarization layer 150 is selected from, but not limited to, a one or more stacked structure formed by one or more of polyimide, polyacrylic acid, or polysiloxane, and has a thickness of 1500-3000 nm. In this embodiment Preferably, the polyimide layer has a thickness of 2000 nm.
[0061] The auxiliary conductive layer 220 and the first electrode 161 are formed of the same material in the same layer, and are directly disposed on the electrode power line 210, and expose a part of the electrode power line 210; the second electrode 163 extends to the non-display area 2 and continuously covers the surface of the auxiliary conductive layer 220 away from the electrode power line 210 and the exposed surface of the electrode power line 210.
[0062] The planarization layer 150 is directly provided with a pixel defining layer 170 covering the first electrode 161, and the organic light emitting layer 162 is formed on the first through hole through a third through hole provided in the pixel defining layer 170. On the electrode 161.
[0063] The second electrode 163 is directly disposed on the pixel defining layer 170 and covers the organic light-emitting layer 162 formed on the first electrode 161; the second electrode 163 also extends to the non-display area 2, And continuously cover the auxiliary conductive layer 220 and the electrode power line 210.
[0064] In this embodiment, the second electrode 163 is further provided with an encapsulation layer 180 for sealing the organic light emitting display device.
[0065] In this embodiment, the capacitor lower plate 141 and the gate layer 133 in the capacitor are formed of the same material in the same layer, and the capacitor upper plate 142 in the capacitor is formed with the source/drain electrode layer It is formed of the same material in the same layer.
[0066] As another embodiment of the present invention, the capacitor lower plate 141 and the capacitor upper plate 142 in the capacitor can also be formed independently. In a polysilicon thin film transistor, the capacitor lower plate 141 or the capacitor upper plate 142 can be The semiconductor layer in the polysilicon thin film transistor is prepared in the same layer, and the polarization is achieved by ion implantation; all of the above can achieve the purpose of the present invention and belong to the protection scope of the present invention.
[0067] The manufacturing method of the organic light emitting display device includes the following steps:
[0068] S1. A buffer layer 120 is formed on the substrate 110. The semiconductor layer 131, the first insulating layer 132, the gate layer 133 and the second insulating layer 134 in the thin film transistor are sequentially formed in the vertical direction of the display area 1. The first insulating layer 132 and the second insulating layer 134 extend to the non-display area 2.
[0069] The preparation method of the buffer layer 120 is selected from but not limited to chemical vapor deposition (CVD). In this embodiment, plasma enhanced chemical vapor deposition (PECVD) is preferred.
[0070] The method for preparing the semiconductor layer 131 is as follows: first deposit a 50nm amorphous silicon layer by PECVD method, and use laser crystallization method to convert the amorphous silicon layer into a polysilicon layer after dehydrogenation treatment.
[0071] The method for preparing the first insulating layer 132 is selected from but not limited to chemical vapor deposition (CVD). In this embodiment, plasma enhanced chemical vapor deposition (PECVD) is preferred.
[0072] The method for preparing the gate layer 133 is as follows: using metal Mo as a target, using magnetron sputtering to deposit a layer of Mo metal layer on the first insulating layer, and then removing the Mo through photolithography and dry etching processes. The metal layer is patterned to form a gate layer 133.
[0073] The preparation method of the second insulating layer 134 is selected from, but not limited to, chemical vapor deposition (CVD). In this embodiment, plasma enhanced chemical vapor deposition (PECVD) is preferred.
[0074] S2. Through an inductively coupled plasma (ICP) etching process, two fifth through holes that penetrate the first insulating layer 132 and the second insulating layer 134 and expose the semiconductor layer 131 are formed, and the fifth through holes are respectively provided On both sides of the gate layer 133, a first metal layer covering the display area 1 and the non-display area 2 is directly formed on the second insulating layer 134, and patterned to form the source electrode 135, the drain electrode 136, and the electrode power supply line 210 , The source electrode 135 and the drain electrode 136 are in contact with the semiconductor layer 131 respectively.
[0075] S3. Through a coating process, a planarization layer 150 covering the source electrode 135, the drain electrode 136 and the electrode power supply line 210 is directly formed on the second insulating layer 134, and patterned by a photolithography process, on the source electrode 135 or the drain electrode 136 A first through hole is formed vertically above the planarization layer 150 to expose the surface of the source electrode 135 or the drain electrode 136, and a second through hole is formed vertically above the electrode power line 210 to penetrate the planarization layer 150 to expose the electrode power line Part or all of the upper surface of 210.
[0076] S4. A second metal layer covering the display area 1 and the non-display area 2 is directly formed on the planarization layer 150 by a magnetron sputtering process, and patterned by a wet etching process to form a first electrode 161 in the display area 1. An auxiliary conductive layer 220 is formed in the non-display area 2; the first electrode 161 extends to cover the sidewall of the first through hole and is electrically connected to the source electrode 135 or the drain electrode 136, and the auxiliary conductive layer 210 extends to cover the second through hole On the sidewalls of the device and electrically connected to the electrode power line 210.
[0077] S5: Partially etch the auxiliary conductive layer 220 directly provided on the electrode power line 210 through a wet etching process to expose the electrode power line 210.
[0078] S6. The pixel defining layer 170 covering the first electrode 161 and the auxiliary conductive layer 220 is formed on the second metal layer by a coating process, and patterned by a photolithography process to form a third through hole exposing the first electrode 161 and an exposure auxiliary The conductive layer 220 and the fourth through hole of the electrode power line 210.
[0079] S7, forming an organic light-emitting layer 162 covering the first electrode 161 directly on the pixel defining layer 170 of the display area 1 by an evaporation process.
[0080] S8. The second electrode 163 covering the organic light-emitting layer 162, the auxiliary conductive layer 220 and the electrode power line 210 is directly formed on the pixel defining layer 170 by an evaporation process.
[0081] S9. An encapsulation layer 180 is provided on the second electrode 163 through a glass frit encapsulation process to encapsulate the organic light emitting display device.
