Preparation method of shallow trench isolation structure
A technology of isolation structure and shallow trench, which is applied in the field of preparation of shallow trench isolation structure, can solve problems such as critical dimension reduction, affecting device performance, and affecting device saturation current, so as to avoid void or gap defects, reduce critical dimension, The effect of reducing consumption
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2015-07-15
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a shallow trench isolation structure. Background technique
[0002] With the development of integrated circuits, modern CMOS chips usually integrate millions of active devices (ie, NMOS transistors and PMOS transistors) on a common silicon substrate material, and then realize various complex circuits through specific connections. Logic functions or analog functions, except for these specific functions, in the design process of the circuit, it is usually assumed that there is generally no other interaction between different devices. Therefore, it is necessary to be able to isolate devices in integrated circuit manufacturing, which requires isolation technology.
[0003] With the development of devices to deep sub-micron, the isolation technology has developed from a local oxidation (Local Oxidation of Silicon, LOCOS) process to a shallow trench is...
Examples
Embodiment Construction
[0031] In order to make the purpose and features of the present invention more obvious and understandable, the specific implementation of the present invention will be further described below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments. The following will be combined with figure 1 and Figures 2A to 2F The preparation method of the shallow trench isolation structure is further described in detail with specific embodiments. in, Figure 2A It is a schematic cross-sectional view of the device structure after silicon nitride is deposited on the active region of the semiconductor substrate, Figure 2B It is a schematic cross-sectional view of the device structure after trench etching in the semiconductor substrate, Figure 2C It is a schematic cross-sectional view of the device structure after the silicon nitride post-pull process, Figure 2D It is a sc...