Preparation method of shallow trench isolation structure

A technology of isolation structure and shallow trench, which is applied in the field of preparation of shallow trench isolation structure, can solve problems such as critical dimension reduction, affecting device performance, and affecting device saturation current, so as to avoid void or gap defects, reduce critical dimension, The effect of reducing consumption

CN104779195AInactive Publication Date: 2015-07-15SHANGHAI HUALI MICROELECTRONICS CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2015-07-15
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention provides a preparation method of a shallow trench isolation structure. After a linear oxidation layer is formed in a trench, a linear amorphous silicon layer is introduced to consume H2O and other oxygen-containing groups generated in a subsequent water steam annealing step for an isolation medium layer, and diffusion of the formed H2O and the other oxygen-containing groups to a semiconductor substrate is further stopped; during water steam annealing of the linear amorphous silicon layer, the semiconductor substrate on the side wall of the trench is replaced, and the H2O and the other oxygen-containing groups are consumed and completely converted into SiO2 to be part of the isolation medium layer in the trench, so that oxidation of a boundary of an active area of the side wall of the trench in the water steam annealing process can be avoided, the material consumption of the semiconductor substrate on the side wall of the trench is reduced, the decrease of the critical dimensions (AA CD) of the active area is reduced, and meanwhile, the defect of forming of a cavity or a gap inside an isolation medium filled in the trench is avoided.
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Description

technical field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a shallow trench isolation structure. Background technique

[0002] With the development of integrated circuits, modern CMOS chips usually integrate millions of active devices (ie, NMOS transistors and PMOS transistors) on a common silicon substrate material, and then realize various complex circuits through specific connections. Logic functions or analog functions, except for these specific functions, in the design process of the circuit, it is usually assumed that there is generally no other interaction between different devices. Therefore, it is necessary to be able to isolate devices in integrated circuit manufacturing, which requires isolation technology.

[0003] With the development of devices to deep sub-micron, the isolation technology has developed from a local oxidation (Local Oxidation of Silicon, LOCOS) process to a shallow trench is...

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Embodiment Construction

[0031] In order to make the purpose and features of the present invention more obvious and understandable, the specific implementation of the present invention will be further described below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments. The following will be combined with figure 1 and Figures 2A to 2F The preparation method of the shallow trench isolation structure is further described in detail with specific embodiments. in, Figure 2A It is a schematic cross-sectional view of the device structure after silicon nitride is deposited on the active region of the semiconductor substrate, Figure 2B It is a schematic cross-sectional view of the device structure after trench etching in the semiconductor substrate, Figure 2C It is a schematic cross-sectional view of the device structure after the silicon nitride post-pull process, Figure 2D It is a sc...