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Semiconductor process for film planarization

A planarization and semiconductor technology, applied in the field of semiconductor device preparation, can solve problems such as contact edge fracture, instability, and graphene film structure damage

Inactive Publication Date: 2015-08-26
BEIJING UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the metal formed by evaporation has a high deposition rate, it cannot deposit metal alloys. At the same time, the amount of evaporated atoms or molecules is large and the speed is unstable, which will lead to poor adhesion between the metal and the substrate, and the whole process is prone to damage to graphite. The film structure of ene is damaged
Therefore, the metal structure can be made by sputtering first, and then the graphene is transferred to the substrate with the metal structure, but at this time, if the sputtered metal is too thick, the gap between the thickness of the graphene film is too large , will cause the graphene and the metal to be incomplete contact, or even break at the contact edge

Method used

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  • Semiconductor process for film planarization
  • Semiconductor process for film planarization
  • Semiconductor process for film planarization

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0063] Embodiment 1: applied in the photodetector of graphene

[0064] S1 After cleaning the silicon wafer with the insulating dielectric layer, the pattern of the gate electrode is formed by photolithography, such as diagram 2-1 , 2-2 , as shown in 2-3;

[0065] S2 uses the photoresist on the device as a mask, ICP etching for 50s, the structure after etching is as follows Figure 2-4 shown;

[0066] S3 Select the etching parameters, remove the glue after the etching is completed, and measure the etched depth with a step meter, which is about 90nm;

[0067] S4 Considering the measurement error, it is decided to sputter metal Ti / Au 15 / 70nm. At this time, the thickness of the metal can roughly fill the groove etched in step 3, as Figure 2-5 shown;

[0068] S5 peels off the excess metal part, after the stripping is completed, if Figure 2-6 , Figure 2-6 The metal material (4) sputtered in is the gate electrode;

[0069] S6PECVD growth of 300nm SiO 2 as an insulating l...

Embodiment 2

[0081] Embodiment 2: be applied in the field effect device of graphene

[0082] S1 cleans the silicon wafer with the insulating dielectric layer, shakes the glue, and prepares for photolithography to form the gate electrode, such as Figure 3-1 , 3-2 ;

[0083] S2 photolithography forms the gate electrode pattern, such as Figure 3-3 shown;

[0084] S3 Select the etching parameters, use the photoresist on the silicon wafer as a mask, ICP etching for 80s, the structure after etching is as follows Figure 3-4 shown;

[0085] S4 After the etching is completed, the glue is removed, and the etched depth is measured with a step meter, which is 140nm;

[0086] S5 Considering the measurement error, it is decided to sputter metal Ti / Au 30 / 100nm, at this time, the thickness of the metal can roughly fill up the groove etched in step 3, as Figure 3-5 shown;

[0087] S6 peels off the redundant metal part, and forms the required gate electrode structure after the stripping is comple...

Embodiment 3

[0096] Embodiment 3: Apply to Hall effect to measure the mobility of graphene

[0097] After S1 cleans the silicon wafer with the insulating dielectric layer, it is prepared for photolithography, such as Pic 4-1 shown;

[0098] S2 throws the glue to photoetch the electrode pattern, such as Figure 4-2

[0099] S3 lithography, resulting in Figure 4-3 graphic of the structure;

[0100] S4 uses the photoresist on the silicon wafer as a mask, ICP etching for 35s, the structure after etching is as follows Figure 4-4 shown;

[0101] S5 Select the etching parameters, remove the glue after the etching is completed, and measure the etched depth with a step meter, which is 65nm;

[0102] S6 Considering the measurement error, it is decided to sputter metal Ti / Au 10 / 45nm, at this time, the thickness of the metal can roughly fill up the groove etched in step 3, as Figure 4-5 shown;

[0103] S7 strips off the excess metal with acetone so that the Figure 4-6 structure shown.

...

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Abstract

A semiconductor process for film planarization is disclosed. In a conventional process of producing semiconductors with graphene films, the films are usually damaged severely. The semiconductor process combines lithography and sputtering technologies and employ inductively coupled plasma (ICP) to ensure the complete contact between the graphene films and metallic structured. The semiconductor process improves the adhesiveness of metal and a substrate, may not damage a graphene film structure and substantially improves the reliability and stability of a semiconductor device.

Description

technical field [0001] The invention belongs to the field of semiconductor device preparation, and in particular relates to a thin film planarization semiconductor process. Background technique [0002] The processing technology of semiconductor devices is mainly divided into planar technology and bulk technology. Bulk technology requires the size of the device to be large enough, and it is not conducive to precise control of the processing size. Especially when it comes to thin film technology, due to the steps formed by different heights on the device, it will A portion of the film is suspended below the section where the film contacts the steps, which can easily lead to breakage or damage of the film, seriously affecting the structure and stability of the device. [0003] Graphene is a new type of carbon material with zero band gap, high mobility, low resistivity and high light transmission, and its thickness is only 0.34nm. Using its energy band structure and related pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/033H01L21/203H01L21/3065
CPCH01L21/033H01L21/2033H01L21/3065H01L31/028
Inventor 徐晨刘奇孙捷许坤
Owner BEIJING UNIV OF TECH
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