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A kind of preparation method of semiconductor device

A semiconductor and device technology, which is applied in the field of semiconductor device preparation, can solve the problems affecting the consistency of the fin outline and fin structure spacing, and achieve the effects of low wet etching rate, simple process and integration method, and easy control

Active Publication Date: 2018-03-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the SADP process technology, complex mask stacks are widely studied, but many problems arise, such as how to maintain the conformality of the pre-fin structure after the dummy core etch during the fin preparation process, and The deformability of the spacer layer formed on the pre-fin structure, the above factors all seriously affect the prepared fin profile and the consistency of the fin structure pitch

Method used

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  • A kind of preparation method of semiconductor device
  • A kind of preparation method of semiconductor device
  • A kind of preparation method of semiconductor device

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Embodiment Construction

[0047] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0048] For a thorough understanding of the present invention, a detailed description will be presented in the following description to illustrate the semiconductor device and the method of manufacturing the same according to the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

[0049] It shou...

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Abstract

The present invention relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor substrate on which a self-aligned double-pattern mask stack is formed, and the self-aligned double-pattern mask stack includes A hard mask layer, a stop layer, and a dummy core material layer are sequentially formed; patterning the dummy core material layer to form a plurality of virtual cores isolated from each other; forming spacers on the sidewalls of the dummy cores; removing all The virtual core, retaining the spacer; using the spacer as a mask, etching the stop layer and the hard mask layer to transfer the pattern to the hard mask layer; using the hard mask The layer is a mask to etch a portion of the semiconductor substrate to form a plurality of fins in the semiconductor substrate. The advantage of the present invention is that a state-of-the-art fin structure can be prepared by selecting a simplified self-aligned mask stack and a simple process.

Description

technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to a method for preparing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, since the semiconductor industry has advanced to the nanotechnology process node in pursuit of high device density, high performance and low cost, the fabrication of semiconductor devices is limited by various physical limits. [0003] Manufacturing and design challenges as CMOS devices continue to shrink have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, the FinFET device has more superior performance in terms of channel control and reducing shallow ch...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027H01L21/336
Inventor 丁士成
Owner SEMICON MFG INT (SHANGHAI) CORP
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