Substrate having electrical interconnection structure and fabrication method thereof

A technology of electrical connection and electrical contact, applied in the field of substrates with electrical connection structures and their manufacturing methods, capable of solving problems such as poor yield rate of semiconductor packages 1', easy residue of adhesive material 160, poor bonding, etc.
CN105023906AActive Publication Date: 2015-11-04SILICONWARE PRECISION IND CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SILICONWARE PRECISION IND CO LTD
Publication Date
2015-11-04

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Abstract

A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
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Description

technical field

[0001] The present invention relates to a substrate with an electrical connection structure, in particular to the improved bonding between electrical contact pads and conductive bumps. Background technique

[0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. Technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM), etc. Crystal-type packaging modules, or three-dimensional stacking of chips into a three-dimensional integrated circuit (3D IC) chip stacking technology, etc.

[0003] The current three-dimensional integrated circuit (3D IC) chip stacking technology, by adding a silicon interposer between the packaging substrate and the semiconductor chip, enables the packaging substrate to be combined with the semiconductor chip with high wiring density electrode...

Claims

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