Backside illuminated image chip module structure and fabrication method thereof

Abstract

The invention discloses a backside illuminated image chip module structure and a fabrication method thereof. The fabrication method comprises the following steps of: 1) backside illuminated (BSI) chip packaging, in which a non through silicon vias (TSV) wafer level packaging process is used for BIS chip package; 2) analog-digital converter / image single processor (ISP) chip package; 3) BSI chip and ADC / ISP chip lamination, in which an inversed packaging technique and a surface mounting technology are used for laminating the packaged BIS chip, a soft board and some auxiliary small devices on the ADC / ISP chip or a silicon-base substrate; and 4) lens module installation to finally form an image chip module. By the backside illuminated image chip module structure and the fabrication method thereof, the stress problem between the BSI chip and the soft board is solved, the volume of the whole module is shortened, the circuit design of the soft board is simplified, and the comprehensive cost of the module is reduced.

Description

technical field [0001] The invention belongs to image chip packaging technology, in particular to a back-illuminated image chip module structure and a manufacturing method thereof. Background technique [0002] At present, the packaging structure and process of the back-illuminated image chip (BSI chip) module have the following disadvantages: [0003] 1) Existing back-illuminated imaging chips are produced using passive silicon wafers as the carrier board. After entering the packaging neighborhood, TSV through holes need to be made on the passive carrier board to realize the electrical connection of the package, and the cost is relatively high; [0004] 2) The existing back-illuminated image chip integrates the photosensitive module and image processing module (such as ADC or ISP chip) into one chip, resulting in a small photosensitive area and poor imaging effect under the same chip size; the same photosensitive area and effect Under the conditions, the chip size is large...

AI Technical Summary

Problems solved by technology

[0003] 1) Existing back-illuminated imaging chips are produced using passive silicon wafers as the carrier board. After entering the packaging neighborhood, TSV through holes need to be made on the passive carrier board to realize the electrical connection of the package, and the cost is relatively high;

[0004] 2) The existing back-illuminated image chip integrates the photosensitive module and image processing module (such as ADC or ISP chip) into one chip, resulting in a small photosensitive area and poor imaging effect under the same chip size; the same photosensitive area and effect Under the conditions, the chip size is large, and it is difficult to meet the needs of consumer electronics for small and thin packages; and the circuit board has high stress and complex structure;

[0005] 3) Currently, TSV packaging on ADC or ISP chips and back-illuminated imaging chips are stacked and packaged at a high cost

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