Fabrication method for wafer-level fan-out package

Abstract

The invention discloses a fabrication method for a wafer-level fan-out package. The fabrication method comprises the following steps of mounting chips on the upper surface of a substrate by using a binding agent; carrying out plastic packaging and forming on the upper surface of the substrate and packaging the chips by a plastic package material layer; coating a dielectric material on the upper surface of the plastic package material layer to form a dielectric layer; removing the dielectric layer corresponding to input-output end positions of the chips and then forming leading-out lines and welding balls on removal parts; thinning along the lower surface of the substrate, removing the substrate, the binding agent, a part of plastic package material layer and the lower surfaces of the chips, and finally leading grinding surfaces to be reserved at chip setting positions to form a package semi-finished product; and cutting the package semi-finished product along a cutting line between two adjacent chips on the package semi-finished into single package structures. According to the fabrication method, the fabrication process steps of the fan-out package can be greatly reduced, the package cost of the fan-out package is greatly reduced, and meanwhile, the package reliability is ensured.

Description

technical field [0001] The invention discloses a method for manufacturing wafer-level fan-out packaging, which belongs to the technical field of microelectronic packaging. Background technique [0002] With the development of people's requirements for electronic products in the direction of miniaturization, multi-function, and environmental protection, people strive to make electronic systems smaller and smaller, with higher integration and more functions. , resulting in many new technologies, new materials and new designs, among which fan-out packaging technology is a typical representative of these technologies. [0003] As a widely used single-chip packaging technology, traditional packaging has gradually shown the disadvantages of low packaging efficiency and rising costs. As a new type of packaging method, wafer-level packaging is widely used in the industry because it can greatly reduce the size of chip packaging. Existing BGA packaging technologies are limited by th...

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Problems solved by technology

However, its disadvantages are also obvious. In the design of its process technology, only the process method of chip function facing down is considered. This application greatly limits the products with function facing up; in addition, this technology needs to be applied to temporary keys. Therefore, it is also very difficult to calculate the cost of the final fan-out package, which directly leads to the high production cost of this packaging technology.

[0005] The research on fan-out packaging technology is still going on. Due to the various unfavorable factors of these process methods, it has a great impact on the yield and reliability of the product, as well as the final shipping price.

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