Fabrication method for wafer-level fan-out package
A technology of manufacturing method and packaging method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the high cost of packaging technology, the impact of final shipping price, and the difficulty in calculating the cost of fan-out packaging. and other problems to achieve the effect of reducing packaging costs, ensuring reliability, and reducing process steps
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Embodiment 1
[0031] A method for manufacturing wafer-level fan-out packaging includes the following steps:
[0032] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is silicon and the thickness is 100um, and the material of the adhesive 7 is epoxy resin and the thickness 5um, such as figure 1 shown;
[0033] b. A plastic sealing material layer 2 is formed on the upper surface of the substrate 6 by a conventional filling process. The plastic sealing material layer 2 encapsulates the chip 1, and the input and output terminals of the chip 1 are exposed. The material of the plastic sealing material layer 2 is a resin with epoxy resin as the main body ,Such as figure 2 shown;
[0034] c. Coating a dielectric material on the upper surface of the plastic packaging material layer 2 to form a dielectric layer 4, the dielectric layer 4 is made of silicon dioxide and has a ...
Embodiment 2
[0039] A method for manufacturing wafer-level fan-out packaging includes the following steps:
[0040] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is ceramic and the thickness is 400um, and the material of the adhesive 7 is silicon dioxide. The main liquid substance with a thickness of 20um, such as figure 1 shown;
[0041] b. A plastic encapsulation material layer 2 is formed on the upper surface of the substrate 6 by a conventional spraying process, and the plastic encapsulation material layer 2 encapsulates the chip 1, and the input and output ends of the chip 1 are exposed, such as figure 2 shown;
[0042] c. Dielectric material is coated on the upper surface of the plastic sealing material layer 2 to form a dielectric layer 4. The material of the dielectric layer 4 is phenol resin and the thickness is 5um, and a layer of protective layer 5 i...
Embodiment 3
[0047] A method for manufacturing wafer-level fan-out packaging includes the following steps:
[0048] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is sapphire and the thickness is 700um, and the material of the adhesive 7 is silicon dioxide. The main membranous substance with a thickness of 40um, such as figure 1 shown;
[0049] b. A plastic sealing material layer 2 is formed on the upper surface of the substrate 6 through a conventional laminating process, and the plastic sealing material layer 2 encapsulates the chip 1, and the input and output ends of the chip 1 are exposed, as shown in FIG. figure 2 shown;
[0050] c. Dielectric material is coated on the upper surface of the plastic packaging material layer 2 to form a dielectric layer 4. The material of the dielectric layer 4 is polyimide and the thickness is 15um, and a layer of protection ...
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