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Fabrication method for wafer-level fan-out package

A technology of manufacturing method and packaging method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the high cost of packaging technology, the impact of final shipping price, and the difficulty in calculating the cost of fan-out packaging. and other problems to achieve the effect of reducing packaging costs, ensuring reliability, and reducing process steps

Inactive Publication Date: 2015-11-25
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, its disadvantages are also obvious. In the design of its process technology, only the process method of chip function facing down is considered. This application greatly limits the products with function facing up; in addition, this technology needs to be applied to temporary keys. Therefore, it is also very difficult to calculate the cost of the final fan-out package, which directly leads to the high production cost of this packaging technology.
[0005] The research on fan-out packaging technology is still going on. Due to the various unfavorable factors of these process methods, it has a great impact on the yield and reliability of the product, as well as the final shipping price.

Method used

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  • Fabrication method for wafer-level fan-out package
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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] A method for manufacturing wafer-level fan-out packaging includes the following steps:

[0032] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is silicon and the thickness is 100um, and the material of the adhesive 7 is epoxy resin and the thickness 5um, such as figure 1 shown;

[0033] b. A plastic sealing material layer 2 is formed on the upper surface of the substrate 6 by a conventional filling process. The plastic sealing material layer 2 encapsulates the chip 1, and the input and output terminals of the chip 1 are exposed. The material of the plastic sealing material layer 2 is a resin with epoxy resin as the main body ,Such as figure 2 shown;

[0034] c. Coating a dielectric material on the upper surface of the plastic packaging material layer 2 to form a dielectric layer 4, the dielectric layer 4 is made of silicon dioxide and has a ...

Embodiment 2

[0039] A method for manufacturing wafer-level fan-out packaging includes the following steps:

[0040] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is ceramic and the thickness is 400um, and the material of the adhesive 7 is silicon dioxide. The main liquid substance with a thickness of 20um, such as figure 1 shown;

[0041] b. A plastic encapsulation material layer 2 is formed on the upper surface of the substrate 6 by a conventional spraying process, and the plastic encapsulation material layer 2 encapsulates the chip 1, and the input and output ends of the chip 1 are exposed, such as figure 2 shown;

[0042] c. Dielectric material is coated on the upper surface of the plastic sealing material layer 2 to form a dielectric layer 4. The material of the dielectric layer 4 is phenol resin and the thickness is 5um, and a layer of protective layer 5 i...

Embodiment 3

[0047] A method for manufacturing wafer-level fan-out packaging includes the following steps:

[0048] a. The chip 1 is mounted on the upper surface of the substrate 6 through the adhesive 7, the input and output ends of the chip 1 face upward, the material of the substrate 6 is sapphire and the thickness is 700um, and the material of the adhesive 7 is silicon dioxide. The main membranous substance with a thickness of 40um, such as figure 1 shown;

[0049] b. A plastic sealing material layer 2 is formed on the upper surface of the substrate 6 through a conventional laminating process, and the plastic sealing material layer 2 encapsulates the chip 1, and the input and output ends of the chip 1 are exposed, as shown in FIG. figure 2 shown;

[0050] c. Dielectric material is coated on the upper surface of the plastic packaging material layer 2 to form a dielectric layer 4. The material of the dielectric layer 4 is polyimide and the thickness is 15um, and a layer of protection ...

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Abstract

The invention discloses a fabrication method for a wafer-level fan-out package. The fabrication method comprises the following steps of mounting chips on the upper surface of a substrate by using a binding agent; carrying out plastic packaging and forming on the upper surface of the substrate and packaging the chips by a plastic package material layer; coating a dielectric material on the upper surface of the plastic package material layer to form a dielectric layer; removing the dielectric layer corresponding to input-output end positions of the chips and then forming leading-out lines and welding balls on removal parts; thinning along the lower surface of the substrate, removing the substrate, the binding agent, a part of plastic package material layer and the lower surfaces of the chips, and finally leading grinding surfaces to be reserved at chip setting positions to form a package semi-finished product; and cutting the package semi-finished product along a cutting line between two adjacent chips on the package semi-finished into single package structures. According to the fabrication method, the fabrication process steps of the fan-out package can be greatly reduced, the package cost of the fan-out package is greatly reduced, and meanwhile, the package reliability is ensured.

Description

technical field [0001] The invention discloses a method for manufacturing wafer-level fan-out packaging, which belongs to the technical field of microelectronic packaging. Background technique [0002] With the development of people's requirements for electronic products in the direction of miniaturization, multi-function, and environmental protection, people strive to make electronic systems smaller and smaller, with higher integration and more functions. , resulting in many new technologies, new materials and new designs, among which fan-out packaging technology is a typical representative of these technologies. [0003] As a widely used single-chip packaging technology, traditional packaging has gradually shown the disadvantages of low packaging efficiency and rising costs. As a new type of packaging method, wafer-level packaging is widely used in the industry because it can greatly reduce the size of chip packaging. Existing BGA packaging technologies are limited by th...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/56H01L21/60
CPCH01L21/50H01L21/56H01L21/568H01L24/85H01L24/94H01L2224/85H01L2224/94H01L2924/1017H01L24/19H01L24/96H01L2224/04105H01L2224/12105H01L2924/18162H01L2924/3511
Inventor 姜峰陆原
Owner NAT CENT FOR ADVANCED PACKAGING
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