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Method for reducing silicon loss

A polysilicon layer and trench technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems affecting the performance of flash memory

Active Publication Date: 2018-09-04
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Silicon loss in the polysilicon layer 103 and the active area severely affects the performance of the flash memory

Method used

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  • Method for reducing silicon loss
  • Method for reducing silicon loss
  • Method for reducing silicon loss

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Embodiment Construction

[0019] In the following description, the present invention is described with reference to various examples. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without these specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0020] Reducing polysilicon gate and active area dimensions becomes...

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Abstract

The invention discloses a method for reducing silicon loss and products manufactured by the method. Through this method, the damage caused to the active area and the polysilicon layer during the etching process can be repaired, and the silicon in the active area and the polysilicon layer will not be excessively consumed. The method includes: forming an active area on a substrate; sequentially forming a pad oxide layer, a polysilicon layer and a silicon nitride layer on the active area; forming a trench in the active area and the polysilicon layer; Nitrogen annealing is performed on the bottom; an oxide lining is formed on the trench surface; and the trench is filled.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular to a method for reducing silicon loss in polysilicon and active regions during the manufacturing process of memory. Background technique [0002] ETOX flash is a type of Erasable Programmable Read-Only Memory (EPROM) that contains a thin tunnel oxide structure, hence the name "ETOX" (Electron Tunnel Oxide Device) flash. [0003] In ETOX flash memory, the floating gate (FG) is used to store electrons to achieve "1" or "0". Floating gates are usually formed of polysilicon. As the size of flash memory continues to shrink, the length of the floating gate and the width of the active area (AA) also continue to shrink. Therefore, the dimensions of the floating gate and the active region have a great influence on the characteristics of the ETOX flash memory. [0004] Figure 1A to Figure 1E A flow chart of etching and trench filling of polysilicon and active regions is show...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L27/11521H01L21/324H10B69/00H10B41/30
Inventor 张冬梅
Owner SEMICON MFG INT (SHANGHAI) CORP