Copper pillar bump packaging structure and manufacturing method thereof
A manufacturing method and packaging structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as increased investment costs and environmental hazards, and achieve environmental protection, reduce pollutant emissions, The effect of excellent electrical conductivity
Active Publication Date: 2019-02-15
SJ SEMICON JIANGYIN CORP
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- Application Information
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Problems solved by technology
However, the waste produced by the electroplating process to prepare the Ni layer is extremely harmful to the environment, and the disposal of the waste electroplating solution increases the investment cost of the product.
Method used
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[0047] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0048] Please refer to attached picture. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be change...
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Abstract
The invention provides a copper pillar bump package structure and a fabrication method thereof. The fabrication method comprises the following steps of firstly, providing a semiconductor substrate provided with metal bonding pads, wherein insulation layers cover the surfaces of the semiconductor substrates; secondly, etching the insulation layers to make the metal bonding pads exposed; and finally, sequentially forming metallic layers, copper pillars, graphene layers and solder cap layers on the metal bonding layers from top to bottom. By fabricating the graphene layers to serve as protective layers of the copper pillars, Ni protective layers in the prior art is substituted, pollutant discharge brought by an electroplating process is reduced, and an environment is protected. Moreover, graphene has excellent electric conductivity, and the copper pillars are protected and simultaneously connected with the outside better to form the package structure with excellent performance.
Description
technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a copper pillar bump packaging structure and a manufacturing method thereof. Background technique [0002] The mobility, lightness and thinness of electronic products have higher and higher requirements on performance, function, size and cost. In order to meet these requirements, in addition to design and manufacturing technology, IC packaging manufacturers are also constantly developing newer and more advanced packaging technologies. Make integration easier to implement. [0003] As we all know, as the development of chip manufacturing process exceeds Moore's Law, the chip density is getting higher and higher, and the spacing between chips is constantly decreasing. Thanks to the superior electrical conductivity, thermal conductivity and reliability of copper materials, copper pillar bumps (CopperPillar Bump) technology gradually replaces tin-lead bump (solder bu...
Claims
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IPC IPC(8): H01L23/488H01L21/60H01L23/492
CPCH01L23/488H01L24/82H01L24/83H01L2224/76H01L2224/11
Inventor 汤红林正忠
Owner SJ SEMICON JIANGYIN CORP