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A method for obtaining large-area ferroelectric thin film transistor array fabrication process

A transistor array and ferroelectric thin film technology, which is applied in the research field of large-area transistor arrays, can solve the problems of expensive large-area substrates and high experimental costs, and achieve the effects of saving experimental costs, reducing experimental difficulty, and high efficiency

Active Publication Date: 2018-12-25
XIANGTAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the other hand, the large-area substrates used to prepare large-area ferroelectric thin films and their devices are usually more expensive, and the ferroelectric thin films and their device substrates with a diameter greater than 5 inches mainly rely on imports, resulting in high experimental costs

Method used

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  • A method for obtaining large-area ferroelectric thin film transistor array fabrication process
  • A method for obtaining large-area ferroelectric thin film transistor array fabrication process
  • A method for obtaining large-area ferroelectric thin film transistor array fabrication process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0033] This example is based on Pt / Ti / SiO 2 Fabrication of 5-inch large-area ZnO / Bi on / Si substrate 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film transistor arrays.

[0034] First, six small-area Pt / Ti / SiO 2 / Si substrate according to figure 2The distribution shown is placed in a 5" large area substrate holder with a silicon wafer shield placed on the back of the substrate holder. The large-area substrate holder is made of Inconel600 nickel-based alloy, and its main components are 73Ni-15Cr-Ti, Al. Then, large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film insulating layer and large-area ZnO semiconductor thin-film channel layer, the target used is a 6-inch large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Target and 6 inch large area ZnO target. Combining the sputtering method and mask technology to prepare Pt source and drain electrodes to form a 5-inch large-area ferroelectric thin film transistor array. Finally, by testing the performance of the large-area fe...

Embodiment 2

[0036] This example is based on Pt / Ti / SiO 2 2-inch large-area ZnO / Bi prepared on / Si substrate 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film transistor arrays.

[0037] Four small-area Pt / Ti / SiO 2 / Si substrate according to Figure 9 The distribution shown is placed in a 5-inch large-area substrate rack, and a silicon wafer baffle is placed on the back of the substrate rack. The materials used for the large-area substrate rack are the same as in Embodiment 1. Then, large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film insulating layer and large-area ZnO semiconductor thin-film channel layer, the target used is a 3-inch large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Target and 3 inch large area ZnO target. Based on the preparation process obtained in Example 1, the preparation parameters were slightly improved to prepare large-area Bi 3.15 Nd 0.85 Ti 3 o 12 A ferroelectric thin-film insulating layer, a large-area ZnO semiconductor thin-film channel layer, a Pt s...

Embodiment 3

[0039] This example is based on SrRuO 3 / SrTiO 3 Preparation of 5-inch large-area ZnO / Bi on a substrate 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film transistor arrays.

[0040] Six small-area SrRuO with a size of 10 mm × 10 mm 3 / SrTiO 3 Substrate according to figure 2 The distribution shown is placed in a 5-inch large-area substrate holder, and a silicon wafer baffle is placed on the back of the substrate holder. The material used for the large-area substrate holder is the same as in Example 1. Then, large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Ferroelectric thin film insulating layer and large-area ZnO semiconductor thin-film channel layer, the target used is a 6-inch large-area Bi 3.15 Nd 0.85 Ti 3 o 12 Target and 6 inch large area ZnO target. Based on the preparation process obtained in Example 1, the preparation parameters were slightly improved to prepare large-area Bi 3.15 Nd 0.85 Ti 3 o 12 A ferroelectric thin-film insulating layer, a large-area ZnO sem...

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Abstract

The invention discloses a preparation method for obtaining a large-area ferroelectric film transistor array. The method mainly comprises the following steps of: (1) placing a small-area substrate on a hollow grid substrate position of a large-area substrate frame; (2) arranging a silicon wafer baffle plate identical with the substrate frame in size on the back side of the substrate; (3) utilizing a physical vapor deposition method to successively prepare a ferroelectric film insulating layer and an oxide semiconductor film channel layer on the substrate; (4) utilizing the physical vapor deposition method and a mask technology to prepare a source electrode and a drain electrode on the channel layer, and forming the large-area ferroelectric film transistor array; and (5) testing the performance of the large-area ferroelectric film transistor array, optimizing the technology parameters in the preparation process of the large-area ferroelectric film transistor array according to the consistency between the transistor unit performance and the array performance, and obtaining the large-area ferroelectric film transistor array meeting the performance requirements and having good consistency and the preparation technology thereof. The method is simple and easy, high in efficiency and low in experiment cost.

Description

technical field [0001] The invention relates to a research method of a large-area ferroelectric thin film transistor array, in particular to a research method of a large-area transistor array used for a liquid crystal display and a high-density non-volatile memory. Background technique [0002] The ferroelectric thin film transistor is a new type of thin film transistor that uses ferroelectric thin film materials instead of traditional insulating layer materials as gate dielectrics. Due to the non-volatile properties of ferroelectric thin films, ferroelectric thin film transistors can be used not only as switching devices in liquid crystal displays, but also as logic units in non-volatile memories. Ferroelectric thin-film transistors have the advantages of non-destructive reading and writing and ultra-fast response, and are a very promising new electronic device. With the development and progress of the semiconductor industry, the requirements for the integration of electro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L27/12
CPCH01L27/1225H01L27/1259
Inventor 钟向丽黄健王金斌李山李波
Owner XIANGTAN UNIV