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Technology integration method for wafer back alignment

A technology of back-alignment and integration method, applied in electrical components, microstructure technology, semiconductor/solid-state device manufacturing, etc., can solve problems such as increasing costs, bringing about compatibility between CMOS and MEMS processes, and reducing manufacturing costs.

Inactive Publication Date: 2016-04-20
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Abstract
  • Description
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Problems solved by technology

Due to the need to add additional lithography facilities, this increases the cost and brings about the process compatibility issues between CMOS and MEMS

Method used

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  • Technology integration method for wafer back alignment
  • Technology integration method for wafer back alignment
  • Technology integration method for wafer back alignment

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Embodiment Construction

[0027] The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0028] It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly show the structure of the present invention for the convenience of description, the structures in the drawings are not drawn according to the general scale, and are drawn Partial magnification, deformation and simplification are included, therefore, it should be avoided to be interpreted as a limitation of the present invention.

[0029] In the following specific embodiments of the present invention, please refer to figure 1 , figure 1 It is a flow chart of the process integration method for wafer back alignment of the present invention; at the same time, please refer to Figure 2-11 , Figure 2-11 is a preferred embodiment of the present invention according to figure 1 Sc...

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Abstract

The invention discloses a technology integration method for wafer back alignment, which comprises: depositing a CMP (chemical mechanical planarization) barrier layer on the front of a substrate, corroding the substrate to form a deep groove serving as an alignment mark, depositing a filler material, filling the deep groove to the full and flattening the deep groove, removing the CMP barrier layer, then continuing to other residual technologies on the front of the substrate, grinding the back of the substrate, exposing the filler material in the deep groove, depositing a masking layer on the back of the substrate, and finishing patterning on the back of the substrate by adopting photoetching and etching technologies. Without adding a double-side alignment photoetching machine, the process integration method can realize the alignment of the back and the front of a wafer by utilizing one same alignment mark, thereby enabling the MEMS (micro-electro-mechanical systems) technology and the CMOS (complementary metal oxide semiconductor) technology to be more compatible and lowering the fabricating cost.

Description

technical field [0001] The invention relates to the technical field of micro-electro-mechanical systems, and more particularly, to a process integration method for wafer back alignment. Background technique [0002] In the CMOS process of conventional large-scale integrated circuits, it usually starts from the lowest layer of the wafer substrate, layer by layer, and pattern it, and continue to alternate. Among them, alignment is required during patterning to prevent the offset of the pattern structure between different layers, and further possible device open-circuit phenomenon. The alignment method is to align the rear layer with the front layer, and to align the front Way. However, in the microelectromechanical system (MEMS) process, it is often necessary to pattern the backside of the substrate, which involves the alignment accuracy between the backside and the frontside. [0003] Alignment is typically performed by a photolithography tool, and the alignment process beg...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C99/00H01L21/68
CPCB81C99/007H01L21/682
Inventor 袁超
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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