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3D NAND flash memory and manufacturing method thereof

A manufacturing method and flash memory technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as development bottlenecks, short circuits or leakage between storage channels and common source terminals, and low yield of three-dimensional NAND flash memory, etc. Achieve the effect of improving yield and preventing distance reduction

Active Publication Date: 2016-05-11
GIGADEVICE SEMICON SHANGHAI INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The manufacturing process of two-dimensional planar flash memory has made great progress. However, due to the limitations of development technology and storage electron density, two-dimensional planar flash memory has encountered a development bottleneck.
see Figure 1G , the reduction of the distance between the storage channel and the common source terminal on the top will easily lead to short circuit or leakage between the storage channel and the common source terminal, and the reduction of the yield rate of the three-dimensional NAND flash memory

Method used

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  • 3D NAND flash memory and manufacturing method thereof
  • 3D NAND flash memory and manufacturing method thereof
  • 3D NAND flash memory and manufacturing method thereof

Examples

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Embodiment 1

[0037] Figure 2A It is a flow chart of a manufacturing method of a three-dimensional NAND flash memory provided in Embodiment 1 of the present invention. see Figure 2A , the manufacturing method, comprising:

[0038] S110, forming an array string unit on the surface of the substrate, forming word line grooves between the array string units, and the word line groove exposes the substrate; the array string unit includes multiple layers of staggered stacked isolation layers and engraved An etch layer, the isolation layer and the etch layer form a storage channel along the stacking direction, and the surface of the substrate adheres to the isolation layer.

[0039] Further, the isolation layer may be silicon oxide, and the etching layer may be silicon nitride. The storage channel is filled with polysilicon.

[0040] S120 , removing the etching layer, and sequentially forming a barrier layer and a metal layer on the exposed surface of the isolation layer and the bottom surfac...

Embodiment 2

[0055] Figure 3A It is a flow chart of a manufacturing method of a three-dimensional NAND flash memory provided by Embodiment 2 of the present invention. The technical solution provided in this embodiment further optimizes the steps S120, S130 and S140 in the first embodiment. see Figure 3A , the manufacturing method specifically includes:

[0056] S210, forming an array string unit on the surface of the substrate, forming word line grooves between the array string units, and the word line groove exposes the substrate; the array string unit includes multiple layers of staggered isolation layers and engraved An etch layer, the isolation layer and the etch layer form a storage channel along the stacking direction, and the surface of the substrate adheres to the isolation layer.

[0057] S220. Remove the etching layer, form a first barrier layer on the exposed surface of the isolation layer and the bottom surface of the word line trench, form a second barrier layer on the su...

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Abstract

The invention discloses a 3D NAND flash memory and a manufacturing method thereof. The manufacturing method comprises the following steps: forming array string elements on the surface of a substrate, forming word line trenches among the array string elements and exposing the word line trenches out of the substrate, wherein each array string unit comprises a plurality of isolation layers and etching layers which are stacked up in an interlacing way, the isolation layers and the etching layers form storage channels along the stacking direction, and the isolation layers are attached to the surface of the substrate; removing the etching layers and sequentially forming barrier layers and metal layers on the surfaces of the exposed isolation layers and the bottoms of the word line trenches; removing part of metal layers and retaining the metal layers among the isolation layers to form a gate electrode; removing the barrier layers from the side walls of the isolation layers, the top end of each array string element and the bottoms of the word line trenches and filling the word line trenches to form a common source line (CSL). According to the technical scheme provided by the invention, the distance between the storage channels and the CSL is maintained to prevent short circuit or current leakage caused by small distance between the storage channels and the CSL and therefore improve the yield of the 3D NAND flash memory.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional NAND flash memory and a manufacturing method thereof. Background technique [0002] Semiconductor memory includes volatile memory and nonvolatile memory. Volatile memory loses its stored contents when power is removed. Non-volatile memory retains stored content even when power is lost. Non-volatile memory includes read-only memory (ROM, Read-onlyMemory), programmable read-only memory (PROM, ProgrammableRead-OnlyMemory), electrically erasable read-only memory (EEPROM, ElectricallyErasableProgrammableRead-OnlyMemory) and flash memory (Flashmemory). Flash memory includes NOR (or not) Flash and NAND (and not) Flash. [0003] The manufacturing process of two-dimensional planar flash memory has made great progress. However, due to the limitations of development technology and storage electron density, two-dimensional planar flash memory has en...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H10B41/35H10B41/20H10B41/27H10B43/27
CPCH10B69/00H10B41/20
Inventor 陈春晖熊涛罗啸刘钊许毅胜舒清明
Owner GIGADEVICE SEMICON SHANGHAI INC