Semiconductor structure forming method

Abstract

The invention provides a semiconductor structure forming method comprising the following steps: providing a semiconductor substrate, wherein a pseudo gate structure and a dielectric layer are formed on the surface of the semiconductor substrate, the pseudo gate structure and the dielectric layer are connected with each other and have flush top surfaces, and the pseudo gate structure includes a gate dielectric layer on the surface of the semiconductor substrate, a protective metal layer on the surface of the gate dielectric layer and a pseudo gate layer on the surface of the protective metal layer; removing the pseudo gate layer to form a trench which exposes the surface of the protective metal layer; performing plasma modification on the exposed protective metal layer to form a modified protective metal layer; and forming a metal gate filling the trench, wherein the top surface of the metal gate is flush with the top surface of the dielectric layer. By using the method, the stability of electrical performance of devices is improved, the failure probability of devices is reduced, the reliability of the metal gate is improved, and the energy consumption of device switches is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are constantly decreasing, and the geometric dimensions of devices are also shrinking continuously following Moore's law. When the size of the semiconductor device is reduced to a certain extent, various problems caused by the semiconductor device approaching the physical limit appear one after another. In the field of semiconductor device manufacturing, the most challenging problem is how to solve the problem of device reliability degradation, which is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer. The method provided by the prior art replaces traditional gate dielectric materials with high-k gate dielectric materials a...

AI Technical Summary

Problems solved by technology

[0004] Although the introduction of gate dielectric layers and metal gates including high-k materials and metal materials can improve the electrical performance of semiconductor devices, it has been found in practical applications that due to the continuous shrinking of the device geometry, the manufacturing process is complicated and difficult to control stably. It is easy to cause the electrical performance of the device to be unstable

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