A kind of semi-polar LED epitaxial structure and preparation method thereof
An epitaxial structure, semi-polar technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of difficult material quality, affecting luminous efficiency, complex process, etc., and achieve the effect of low cost and strong operability
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Embodiment 1
[0038] Please refer to Figure 1~Figure 5 , this embodiment provides a method for fabricating a GaN semipolar LED epitaxial structure, which can avoid the problems of poor growth of semipolar materials and expensive homogeneous semipolar materials. The following technical scheme takes the nano-sapphire graphic substrate as an example, and the manufacturing method includes the following steps:
[0039] Please refer to figure 1 , provide a nano-patterned sapphire substrate 11 (Sapphire), put it into a metal-organic chemical vapor deposition (MOCVD) device and heat it up to 1000-1200°C, and treat it in a hydrogen atmosphere for 3-10 minutes; use a nano-patterned sapphire substrate The bottom (PSS, Patterned Sapphire Substrate) can obtain a regular surface V-shaped pit (pit) array. The pattern line diameter of PSS is 100~1000nm, the pattern height is 300~2000nm, and the pitch is 1 / 5~1 / of the period size. 2. The pattern under this size does not affect the existing chip manufactu...
Embodiment 2
[0045] Please refer to Figure 5 , an LED epitaxial structure provided in this embodiment includes, from bottom to top, a sapphire substrate 11, a buffer layer 12, a nano The semiconductor bottom structure of the V-shaped pit, the semiconductor functional layer 16 including SLs / MQWs / pAlGaN / pGaN / p++ and the electrode structure (not shown in the figure).
[0046] Specifically, the sapphire substrate 11 of this embodiment may be a patterned sapphire substrate (PSS, Patterned Sapphire Substrate), or a flat sapphire substrate (FSS, Flat Sapphire Substrate), and the PSS substrate is preferred in this embodiment , the pattern line diameter is 100~1000nm, the pattern height is 300~2000nm, and the pitch is 1 / 5~1 / 2 of the period size. The pattern under this size does not affect the existing chip manufacturing process to prepare the chip, that is, it does not affect the subsequent chip electrode Preparation and other photolithography processes, if the pattern line size is too small (100...
Embodiment 3
[0051] Please refer to Image 6 , the difference between this embodiment and embodiment 1 is that the surface of the semiconductor functional layer 16 in embodiment 1 has a nano V-shaped pit, while the semiconductor functional layer 26 of this embodiment includes a first semiconductor functional layer 261 and a second semiconductor functional layer 262 , wherein the first semiconductor functional layer 261 includes SLs, MQWs, and pAlGaN, and the growth method is the same as in Embodiment 1, that is, by accelerating the growth rate on the semipolar plane to 5 to 10 times that of the normal polar plane or prolonging the growth time to the normal polar plane. 5 to 10 times the surface of the surface to obtain nano-V-shaped pits on the surface of the first semiconductor functional layer; the second semiconductor functional layer 262 includes pGaN and p++, and adopts the conventional p-type GaN growth mode (the growth temperature is around 950°C, usually into a large amount of H 2...
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