Multi-core multi-threaded processor with precise performance control function

Abstract

A multi-core multi-threaded processor with a precise performance control function comprises an OS-level configuration and monitoring interface, performance record register blocks, a hardware-level supervising thread processing core, resource record register blocks, a thread context register, a central control unit and shared processor hardware. The multi-core multi-threaded processor has the advantages that the N performance record register blocks, the N resource record register blocks and the hardware-level supervising thread processing core are all of a novel system structure, a microarchitecture and an operating mechanism of the multi-core multi-threaded processor according to the design, and explicit regulation and precise control of the performance and resource configuration of multiple threads are achieved; by means of the OS-level configuration and monitoring interface of HLST, an interface is reserved for system collaborative design, and the ubiquitous problems of highlighting the main body and weakening individuals of hardware on common multi-core multi-threaded processors are effectively solved, and the black box effect of OS-level dispatching is effectively overcome.

Description

technical field [0001] The invention relates to a multi-core multi-threading (multi-core multi-threading) processor technology, in particular to a multi-core multi-threading processor technology whose performance can be precisely controlled. The invention belongs to the field of computer system design, and is used for explicit regulation of hardware resources of multi-core and multi-thread computer systems, especially multi-core and multi-thread processors, and precise control of thread performance. The specific application field is the multi-core multi-thread computer system, especially the multi-core multi-thread computer system structure design with high requirements on thread performance, real-time performance and determinism, including the design and implementation of OS-level resource allocation and thread performance control functions. . Background technique [0002] Computer systems have entered the era of on-chip multithreading (CMT) architecture, that is, the era ...

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Problems solved by technology

[0005] (2) The "black box" effect of OS-level scheduling: The OS's performance management of multithreading stops at scheduling selected threads or thread combinations to run on processors. It is difficult to monitor and manage the actual running status of the thread on-chip

[0006] (3) Lack of system-level comprehensive design: lack of system-level monitoring and control mechanisms and methods for the performance and resource allocation of multiple threads running simultaneously on multi-core multi-thread processors, and lack of related system-level collaborative design

[0007] In summary, although multi-core and multi-threading have greatly improved computing performance, there is still a lack of methods, designs, and implementations for precise control of multi-threading performance and resource occupation.

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