New MOSFET package structure and wafer manufacturing method
A packaging structure, wafer-level technology, applied in the direction of electrical components, electrical solid-state devices, circuits, etc., can solve the problems of low yield rate, high cost of through-silicon vias, complex back gold process, etc., to achieve high production efficiency and low packaging cost Low, excellent heat dissipation effect
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[0040] As a preferred embodiment, a wafer-level manufacturing method of a novel MOSFET packaging structure of the present invention comprises the following steps:
[0041] a. Several MOSFET chips 400 are provided, the front side of the MOSFET chip includes a source 401 and a gate 402, the back side of the MOSFET chip includes a drain 403, and a metal layer is deposited on the outer surface of the drain;
[0042] b. A carrier wafer is provided as the substrate 100, and a conductive layer 200 is laid on the front surface of the carrier wafer; the conductive layer is such as a copper metal layer.
[0043] c. Provide a number of metal sheets 500, such as copper sheets, form a pair of the metal sheets and the MOSFET chip, and bond them to the conductive layer of the carrier wafer through conductive materials, wherein the metal layer outside the drain of the MOSFET chip Towards the carrier wafer; during specific implementation, a layer of solder can be printed on the conductive laye...
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