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New MOSFET package structure and wafer manufacturing method

A packaging structure, wafer-level technology, applied in the direction of electrical components, electrical solid-state devices, circuits, etc., can solve the problems of low yield rate, high cost of through-silicon vias, complex back gold process, etc., to achieve high production efficiency and low packaging cost Low, excellent heat dissipation effect

Inactive Publication Date: 2016-08-31
HUATIAN TECH KUNSHAN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The back gold process of this packaging solution is complicated, the yield rate is low, and the cost of using through-silicon via (TSV) technology is high

Method used

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  • New MOSFET package structure and wafer manufacturing method
  • New MOSFET package structure and wafer manufacturing method
  • New MOSFET package structure and wafer manufacturing method

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Embodiment approach

[0040] As a preferred embodiment, a wafer-level manufacturing method of a novel MOSFET packaging structure of the present invention comprises the following steps:

[0041] a. Several MOSFET chips 400 are provided, the front side of the MOSFET chip includes a source 401 and a gate 402, the back side of the MOSFET chip includes a drain 403, and a metal layer is deposited on the outer surface of the drain;

[0042] b. A carrier wafer is provided as the substrate 100, and a conductive layer 200 is laid on the front surface of the carrier wafer; the conductive layer is such as a copper metal layer.

[0043] c. Provide a number of metal sheets 500, such as copper sheets, form a pair of the metal sheets and the MOSFET chip, and bond them to the conductive layer of the carrier wafer through conductive materials, wherein the metal layer outside the drain of the MOSFET chip Towards the carrier wafer; during specific implementation, a layer of solder can be printed on the conductive laye...

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Abstract

The present invention discloses a new MOSFET package structure and a wafer manufacturing method. The package structure comprises a MOSFET chip, the right side of the MOSFET chip includes a source electrode and a grid electrode, and the back side of the MOSFET chip includes a drain electrode; the source electrode and the grid electrode are respectively electrically connected with the second conductor and the third conductor at the right side of the MOSFET chip, a sheet metal and the drain electrode at the back side of the MOSFET chip are bonded on the conduction layer of the substrate through conductive materials, and a first conduction body is made on the sheet metal; and the sheet metal is connected with the first conduction body of the right side of the MOSFET chip. Therefore, the drain electrode at the back side of the MOSFET chip with a vertical structure is led to the right side of the MOSFET to realize the electrical properties of the source electrode, the grid electrode and the drain electrode to be the same side so as to perform wafer package, and large-scale conduction layer ensures good heat radiation effect of the chip; and the silicon through hole TSV process is avoided, so that the technology steps are simplified, and the package cost is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a novel MOSFET packaging structure and a wafer-level manufacturing method thereof. Background technique [0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a field effect transistor that uses electric field effects to control semiconductors. Due to the characteristic of realizing low power consumption voltage control, MOSFET has been widely used in a large number of electronic devices in recent years, including power supplies, automotive electronics, computers and smart phones, and has received more and more attention. [0003] A MOSFET device operates by applying an appropriate voltage to the gate of the MOSFET device, which turns on the device and forms a channel connecting the source and drain of the MOSFET device to allow current to flow. In MOSFET devices, it is desirable to have a low drain-on-source resistance RDS(on) when tu...

Claims

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Application Information

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IPC IPC(8): H01L23/485
CPCH01L24/26H01L2224/29099H01L2224/04105H01L2224/06181H01L2224/12105H01L2224/32225H01L2224/32245H01L2224/73253H01L2224/73267H01L2924/15192
Inventor 于大全姚明军翟玲玲崔志勇
Owner HUATIAN TECH KUNSHAN ELECTRONICS
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