Digital low-level control processor capable of flexibly configuring clock frequency

Abstract

The invention provides a digital low-level control processor capable of flexibly configuring the clock frequency. The processor comprises a multi-path high-speed analog-digital conversion channel, a multi-path high-speed digital-analog conversion channel, a multi-path digital output port, a digital signal processing chip and a clock distribution system. The clock distribution system is used for providing clock signals for the digital signal processing chip and comprises a clock distribution chip and a CPLD chip. The clock distribution chip is used for sending clock signal to the digital signal processing chip according to input reference signals and configuration parameters of a clock distribution chip register, and the CPLD chip is used for setting configuration parameters and storing the configuration parameters. The digital low-level control processor capable of flexibly configuring the clock frequency integrates the clock distribution unit having a register parameter automatic response function and a multi-path fan-out function, the multi-path high-speed analog-digital conversion channel, a two-path high-speed digital-analog conversion channel and the multi-path digital output port, and has the advantages of being small in size, stable, reliable, economical and convenient to maintain.

Description

technical field [0001] The invention relates to a digital low-level control processor, in particular to a digital low-level control processor capable of flexibly configuring clock frequency. Background technique [0002] With the development of my country's science and technology and the improvement of comprehensive national strength, high-energy and high-stability electron accelerators provide experimental conditions for research in multidisciplinary fields. Some medical accelerators, such as proton or heavy ion therapy devices, are also in wide demand. Therefore, low-level controllers with high precision, high stability and high integration came into being. Accelerator high-frequency low-level control technology has gone through three stages: full analog control, digital plus analog control and full digital control. The high-frequency and low-level control of accelerators in the late 1960s and 1990s was all analog control, and the core component was an analog feedback amp...

AI Technical Summary

Problems solved by technology

The digital low-level controller has been matured and widely used in high-quality charged particle accelerators with multiple inserts, high current intensity, low energy dissipation, and low emittance after research by many laboratory scientists. Due to the special requirements for the number of digital conversion channels, motor drive, and communication methods, it is still impossible to find clock distribution with integrated automatic download function, four high-speed analog-to-digital conversion channels, two high-speed digital-to-analog conversion channels, and CPCI ( Compact PCI, a digital signal processor for communication and eight-way digital output ports; it has the function of solidification and singleness, and the problem of complex structure connected by coaxial cables between boards and cards can improve the accuracy and stability control of high-frequency signal amplitude and phase Needs to be improved, insufficient hardware resources, expensive, inconvenient development and maintenance, etc.

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