Self-aligned split gate flash memory device and manufacturing method thereof

Abstract

The invention discloses a self-aligned split gate flash memory device. One unit structure comprises a polysilicon word line, a polysilicon floating gate and source polysilicon, wherein a first floating gate sidewall covers a top surface of the polysilicon floating gate and a first side surface of the polysilicon word line; a second floating gate sidewall is formed on the first side surface of the polysilicon floating gate; the first floating gate sidewalls and the second floating gate sidewalls of two adjacent unit structures define a forming region of the source polysilicon in a self-aligned manner and the width of the bottom of the source polysilicon is defined by each second floating gate sidewall in a self-aligned manner; a second floating gate sidewall material comprises a first oxide layer and a second oxide layer formed by CVD HTO; and the first oxide layer is formed by carrying out thermal oxidation on silicon on the first side surface of the polysilicon floating gate. The invention further discloses a manufacturing method of the self-aligned split gate flash memory device. According to the self-aligned split gate flash memory device and the manufacturing method thereof, the data retention capacity of the device can be improved and good control on the width of the bottom of the source polysilicon and the length of the polysilicon floating gate can be ensured.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a self-aligned split-gate flash memory device; the invention also relates to a self-aligned split-gate flash memory device manufacturing method. Background technique [0002] Such as figure 1 Shown is a schematic cross-sectional view of a cell structure of an existing self-aligned split-gate flash memory device. Taking an N-type device as an example, the cell structure of an existing self-aligned split-gate flash memory device is formed on a P-type doped semiconductor substrate such as On the silicon substrate 101, a coupling oxide layer 102, a polysilicon floating gate (FG) 103, a gate oxide layer 104 and a polysilicon word line 105 are formed on the surface of the semiconductor substrate 101; [0003] A tunnel oxide layer 106 is isolated between the second side of the polysilicon floating gate 103 and the bottom of the first side of the polysilicon wor...

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Problems solved by technology

However, it can be seen from the reaction equation of CVD HTO that there will be Cl ions in the reaction process, so that Cl will also be introduced into the second floating gate sidewall 108, and the presence of Cl may form a leakage path (leakage path). It will affect the quality of the oxide layer and thus affect the DR performance of the device

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