Signal enhancement prescaler

Abstract

The invention relates to a signal enhancement prescaler which is characterized in that the signal enhancement prescaler comprises two signal enhancement source coupling logic triggers; the trigger is provided with two passive devices on the structure of a traditional source coupling logic trigger; the input end of each trigger and a complementary output end thereof are respectively provided with a passive device (a resistor, a capacitor or an inductor, or a combined device which is obtained through combining several types of the devices), thereby increasing the working frequency of the prescaler. The signal enhancement prescaler has main purposes of counteracting the capacitance Cgd of a clock input tube pair and effectively increasing working frequency of the prescaler. The signal enhancement prescaler has advantages of higher working frequency, lower power consumption, wider working range and relatively high sensitivity. The signal enhancement prescaler can be widely applied in a phase-locked loop of a frequency synthesizer and corresponding products in RF fields such as a mobile phone, a Bluetooth product, a mobile communication terminal and a mobile phone TV.

Description

technical field [0001] The invention relates to a signal enhancing prescaler, which belongs to the technical field of integrated circuit design and signal processing. Background technique [0002] The prescaler and VCO (Voltage Controlled Oscillator) occupy most of the power consumption in the communication system, and reducing their power consumption has become the key to reducing the power consumption of the whole system. There are three main types of prescalers: TSPC-based prescalers, source-coupled flip-flop-based prescalers, and lock-injection prescalers. The prescaler based on the TSPC structure adopts single-phase clock technology and requires a rail-to-rail (rail to rail) input signal, which requires a high-current buffer stage, and cannot provide quadrature signals, and consumes a lot of power. Although the injection-locked frequency divider (Injection-locked Frequency Divider) consumes less power, its disadvantages are that the frequency division range is small, a...

AI Technical Summary

Problems solved by technology

The prescaler based on the TSPC structure adopts single-phase clock technology and requires a rail-to-rail (rail to rail) input signal, which requires a high-current buffer stage, and cannot provide quadrature signals, and consumes a lot of power

Although the injection-locked frequency divider (Injection-locked Frequency Divider) consumes less power, its disadvantage is that the frequency division range is small, and the inductor is needed in the composition, the chip occupies a large area, and the process is difficult.

The prescaler based on source-coupled flip-flop has moderate power consumption, large frequency division range, and can generate quadrature signals. The disadvantage is that its power consumption increases rapidly as the operating frequency increases.

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