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Forming method of fin type field-effect tube

A fin field effect transistor and fin technology, which is applied to semiconductor devices, electrical components, circuits, etc., can solve the problem that the electrical performance of the fin field effect transistor needs to be improved, and achieve improved electrical performance, large process window, and optimized electrical performance effect

Active Publication Date: 2017-05-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the electrical performance of the fin field effect transistor formed by the prior art needs to be improved

Method used

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  • Forming method of fin type field-effect tube
  • Forming method of fin type field-effect tube
  • Forming method of fin type field-effect tube

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Experimental program
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Embodiment Construction

[0033] It can be seen from the background art that the electrical performance of the fin field effect transistor formed in the prior art needs to be improved.

[0034] After research, it is found that the pattern density of each area of ​​the substrate is not exactly the same. According to the pattern density of the substrate surface, the substrate includes a pattern dense area (Dense Area) and a pattern sparse area (ISO Area). The pattern density of the fins located on the substrate surface of the dense area is greater than the pattern density of the fins located on the substrate surface of the sparse area.

[0035] The process steps of forming the fins include: providing an initial substrate including a sparse area and a dense area; forming a patterned mask layer on the surface of the initial substrate, and openings are formed in the patterned mask layer, wherein, The opening size in the mask layer above the sparse area is the first opening size, the opening size in the mask...

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Abstract

The invention relates to a forming method of a fin type field-effect tube. The forming method comprises: a substrate including a first region and a second region adjacent to the first region is provided, wherein a plurality of discrete fin parts are formed on the surface of the substrate and the fin parts are arranged at equal intervals; the intervals between the adjacent fin parts are filled with first dielectric layers, wherein the first dielectric layers cover the surfaces of the side walls of the fins; the fin parts in the second area are removed and thus the substrate surface in the second area is exposed; a second dielectric layer is formed on the substrate in the second area, wherein the second dielectric layer also covers the surfaces of the side walls of the first dielectric layers in the first area and the tops of the first dielectric layers are flush with the top of the second dielectric layer; and back etching is carried out to remove the first dielectric layers and the second dielectric layer at the certain thicknesses and thus the partial side wall surfaces of the fin parts in the first area are exposed. According to the forming method, the plurality of fin parts with different graphic densities are formed and the fin parts have excellent feature dimensions and forms, so that the electrical performances of the fin type field-effect tube can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the pheno...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/66795
Inventor 赵海肖芳元
Owner SEMICON MFG INT (SHANGHAI) CORP
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