53results about How to "Avoid loading effect" patented technology

In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

A light-emitting diode array comprising a conductive layer formed on a substrate, separate light-emitting portions formed on the conductive layer, a first electrode formed on at least part of an upper surface of each light-emitting portion, and a second electrode formed on the conductive layer adjacent to the light-emitting portions; the first electrode comprising a common switching electrode matrix; the second electrode comprising a common electrode divided such that one second electrode exists in every block; and at least one of bonding pads extending to the first common electrode and the second common electrode being formed on a bonding portion formed on the conductive layer like an island, whereby the bonding pads are separate from each other.

The invention discloses a method for eliminating load effect of a multi sequence single deposition (MSSD) device. A device for eliminating the load effect of the MSSD device comprises a plurality of heaters. The method for eliminating the load effect of the MSSD device includes the following steps of providing a plurality of virtual wafers, placing the virtual wafers in the deposition device; during a depositing process of the deposition device, placing product wafers on all or part of the heaters, and meanwhile, placing the virtual wafers on the heaters without the product wafers; when the deposition device is cleaned, removing all the product wafers on the heaters, and placing the virtual wafers on all the heaters. By the aid of the method, the load effect of the MSSD device can be eliminated, frequent replacing for the virtual wafers placed in the deposition device is avoided, labor force and cost are saved, and simultaneously service life of the heaters is prolonged.

An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.

A mask includes a substrate, at least a first strip pattern, at least a second strip pattern and an assist pattern. A width of the second strip pattern is substantially larger than a width of the first strip pattern. The assist pattern is disposed in the second strip pattern neighboring the first strip pattern, and the assist pattern does not overlap a center line of the second strip pattern.

A method for forming a fin field effect transistor comprises: providing a substrate, wherein the substrate includes first regions and second regions located between adjacent first regions, a plurality of discrete fins are formed on the surface of the substrate, and the distances between the adjacent fins are the same; fully filling the surface of the substrate between the adjacent fins with a first dielectric layer, wherein the first dielectric layer covers the sidewall surfaces of the fins; removing the first dielectric layer of the second regions to expose the sidewall surfaces of the fins in the second regions; oxidizing the fins of the second regions to convert the fins of the second regions into an oxidizing structure; forming a second dielectric layer on the substrate in the second regions, wherein the second dielectric layer also covers the sidewall surface of the oxidizing structure, and the sidewall surface of the first dielectric layer in the first regions; etching back a part of thickness of the first dielectric layer, the second dielectric layer, and the oxidizing structure. The method forms a number of fins with different pattern densities and with good feature sizes and morphology so as to improve the electrical performance of the fin field effect transistor.

The present application relates to an array substrate. In the fan-out region of the array substrate, first metal lines, second metal lines and common electrode lines insulated from each other are sequentially stacked. On any cross-section of the extension path of the first metal lines , the first metal line includes a first end point and a second end point in the first direction, the second metal line does not exceed the first end point in the first direction, and the common electrode line is The first direction does not exceed the second endpoint. The second metal line and the common electrode line form a cross-stacked structure in the first direction, which can avoid the conduction of the two in the case of poor cutting, and ensure that the array substrate will not be short-circuited. The present application also relates to a liquid crystal display and an electronic device equipped with the above-mentioned array substrate.

The invention discloses an integrated method of a raise source leakage structure complementary metal-oxide-semiconductor transistor (CMOS) and a Bipolar device. The integrated method of the raise source leakage structure CMOS and the Bipolar device comprises forming a grid structure on a traditional shallow groove isolation structure, wherein a certain etch quantity of a silicon substrate is caused by side wall etch, using selective epitaxy to develop polycrystalline silicon in a source leakage area so as to form a raise source leakage area, depositing dielectric film again to protect a CMOS area; forming a polycrystalline silicon side wall after base polycrystalline silicon etch is carried out, removing dielectric film of the CMOS area, and keeping dielectric film under the polycrystalline silicon side wall; using emitting electrode polycrystalline silicon as expansion of the raise source leakage area to a shallow trench isolation (STI) area and a connecting line of a CMOS local area, coating a layer of filling materials after imaging is carried out, carrying out backward etch on the filling materials and the emitting electrode polycrystalline silicon above the source leakage area, and stopping etch on the dielectric film; at last, removing the filling materials and an etch stopping layer, and finishing source leakage injection, follow-up contact holes and a metal connecting line technology. The integrated method of the raise source leakage structure CMOS and the Bipolar device has the advantages of being capable of effectively reducing the size from an active area to a grid, increasing amount of transistors in unit area, enlarging a technology window, reducing source leakage parasitic capacitance, and improving a short-channel effect.

The present invention provides a method for forming a dual-damascene structure. The method comprises successively forming a barrier layer, a low dielectric constant layer, a first buffer layer, a hardmask layer, and a second buffer layer on the surface of a semiconductor structure in which a metal structure is embedded; etching the second buffer layer and the hard mask layer to form a first trench; etching the first buffer layer and the low dielectric constant layer to form a first via hole; downwards etching the low dielectric constant layer to form a second via hole; integrally etching thefirst via hole and the second via hole to form a second trench; opening the barrier layer to expose the metal structure so as to form the dual-damascene structure. Performing local via hole etching twice can well solve a load effect caused by etching and improve the dual-damascene etching defect, thereby improving the dual-damascene shape. Further, the second trench formed by the integral etchingis favorable for subsequent copper filling, which improves the reliability of the dual-damascene structure.