Integrated method of raise source leakage structure complementary metal-oxide-semiconductor transistor (CMOS) and Bipolar device

Abstract

The invention discloses an integrated method of a raise source leakage structure complementary metal-oxide-semiconductor transistor (CMOS) and a Bipolar device. The integrated method of the raise source leakage structure CMOS and the Bipolar device comprises forming a grid structure on a traditional shallow groove isolation structure, wherein a certain etch quantity of a silicon substrate is caused by side wall etch, using selective epitaxy to develop polycrystalline silicon in a source leakage area so as to form a raise source leakage area, depositing dielectric film again to protect a CMOS area; forming a polycrystalline silicon side wall after base polycrystalline silicon etch is carried out, removing dielectric film of the CMOS area, and keeping dielectric film under the polycrystalline silicon side wall; using emitting electrode polycrystalline silicon as expansion of the raise source leakage area to a shallow trench isolation (STI) area and a connecting line of a CMOS local area, coating a layer of filling materials after imaging is carried out, carrying out backward etch on the filling materials and the emitting electrode polycrystalline silicon above the source leakage area, and stopping etch on the dielectric film; at last, removing the filling materials and an etch stopping layer, and finishing source leakage injection, follow-up contact holes and a metal connecting line technology. The integrated method of the raise source leakage structure CMOS and the Bipolar device has the advantages of being capable of effectively reducing the size from an active area to a grid, increasing amount of transistors in unit area, enlarging a technology window, reducing source leakage parasitic capacitance, and improving a short-channel effect.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit manufacturing, and in particular relates to an integration method of CMOS (complementary metal oxide semiconductor field effect transistor) and Bipolar (bipolar transistor) devices with raised source-drain structure. Background technique [0002] Reducing the design size of the active area (AA) and the gate (gate) can effectively reduce the parasitic capacitance of the source and drain, increase the speed of the device, and at the same time reduce the area of ​​the device, so that there are more devices per unit area. However, this design size is limited by the design size of the contact hole and the process capability of the contact hole registration, and the process window and the device size become two factors that restrict each other. [0003] Another problem is that as the device size continues to shrink, the effective channel length decreases, which is known to cause the short...

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Problems solved by technology

The raised source and drain are generally grown by selective epitaxial silicon single crystal, and then the source and drain junctions are formed by ion implantation. The depth of the source and drain junctions formed in this way will also be correspondingly shallower, thereby improving the short channel effect. This structure Because high-dose implantation is generally relatively shallow, and the diffusion of impurities in silicon single crystals is slow, the height of epitaxial single crystals is limited

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