Hardware Architecture and Computational Flow of Binary Weighted Convolutional Neural Network Accelerator

Abstract

The invention discloses the hardware architecture of a binary weight convolution neural network accelerator and a calculation process thereof. The hardware architecture comprises three double-ended on-chip static random access memories which are used for buffering the binary weight of input neurons and a convolution layer, four convolution processing units capable of controlling calculation parts to complete major convolution calculation operation according to the calculation process, a feature map accumulation unit and a convolutional accumulation array. The feature map accumulation unit and the convolutional accumulation array are used for further processing the operation result of the convolution processing units to acquire a final correct output neuron value. The entire design exchanges data with an off-chip memory via a dynamic random access memory interface. In addition to the hardware architecture, the invention further provides the detailed calculation process which optimizes the hardware architecture and uses four lines of input feature map as a complete calculation unit. According to the invention, input data are reused to the greatest extent; the access of the off-chip memory is eliminated as much as possible; the power consumption of the deep binary convolution neural network calculation can be effectively reduced; a deep network is supported; and the scheme provided by the invention is a reasonable scheme which can be applied to an embedded system of visual application.

Description

technical field [0001] The invention designs the field of computer and electronic information technology, and in particular relates to a hardware architecture and a calculation process of a special accelerator for a binary weighted convolutional neural network. Background technique [0002] The deep convolutional neural network model has made great breakthroughs and successes in many fields such as image classification, action detection, speech recognition and other big data analysis tasks. On the one hand, as the effect of the convolutional neural network becomes better and better, its topology structure is also deepening, and the number of parameters has reached 10 to the 6th power and above, which brings extreme computational complexity. With a big boost, the required computing power has exploded. On the other hand, embedded systems can only provide limited resources, and their power consumption is also limited within a certain range. Although the existing solutions usin...

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Problems solved by technology

[0005] The present invention aims to solve the technical problem of applying convolutional neural networks to power-constrained embedded systems, or at least propose a useful commercial option

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