A kind of semiconductor device and its manufacturing method and electronic device

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method comprises a step S1 of providing a semiconductor substrate, forming an NMOS area and a PMOS area on the semiconductor substrate, wherein each of the NMOS area and the PMOS area is provided with virtual grid electrodes and inter layer dielectrics filling gaps among the virtual grid electrodes, a patterned hard mask layer is formed on the PMOS area in order to make the virtual grid electrodes in the NMOS area be exposed; a step S2 of removing the exposed virtual grid electrodes in the NMOS area to form NMOS virtual openings; a step S3 of carrying out over etching by means of a combination of HBr, NF3 and Ar or a combination of H2 and Ar in order to remove the virtual grid electrodes completely, and selecting Ar to process residues on sidewalls of the virtual openings after the over etching process; a step S4 of repeating the step S3 for at least four times; and a step S5 of removing the residues on the sidewalls of the virtual openings.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the rapid development of microelectronics technology, the core of microelectronics technology - Complementary Metal Oxide Semiconductor (CMOS) technology has become the supporting technology of modern electronic products. In the semiconductor manufacturing process, various materials can be used as the gate electrode and gate dielectric of CMOS devices. Traditional CMOS devices usually use silicon oxynitride (SiON) as the gate dielectric layer, and doped Doped polysilicon is used as the gate electrode material. However, with the continuous improvement of integrated circuit manufacturing technology, the continuous improvement of chip integration, the reduction of technology nodes, and the trend of size change, more and more ad...

AI Technical Summary

Problems solved by technology

There are many problems in the process of removing the dummy gate at present: 1) polymers and / or by-products will be deposited on the sidewalls of the dummy gate opening during the process of removing the dummy gate by dry etching, resulting in poorer boundary contact between NMOS and PMOS

Therefore, in order to maintain the performance of the device, a larger voltage must be applied, and in more serious cases, if the NMOS and PMOS boundaries are opened, it will cause the device to fail

2) In the process of removing the dummy gate, the loss of the interlayer dielectric layer becomes a main parameter, and dry etching and wet etching will consume the interlayer dielectric layer, wherein the consumption of a large amount of the interlayer dielectric layer Can lead to metal residues, affecting the process window of CMP

[0004] In the prior art, a hard mask layer is used to obtain a better line end profile and CD LWR, but in this process the hard mask must be kept sufficiently over-etched to prevent dummy gate residues, but excessive The over-etching of the PMOS device will cause damage to the PMOS device and the loss of more interlayer dielectric layers, and the loss of the interlayer dielectric layer will also cause short circuits between NMOS and PMOS

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