Silicon-on-insulator (SOI) single-port static random access memory unit and a fabrication method thereof
A memory unit, static random technology, applied in static memory, digital memory information, semiconductor/solid-state device manufacturing, etc., can solve problems such as leakage increase, achieve simple manufacturing process, eliminate chip area, and suppress the effect of total dose effect
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Embodiment 1
[0108] The present invention provides a SOI single-port static random access memory unit, please refer to Figure 5 , shown as a schematic diagram of the circuit principle of the SOI single-port SRAM unit, including:
[0109] The first inverter 201 is composed of a first PMOS transistor 2011 and a first NMOS transistor 2012;
[0110] The second inverter 202 is composed of a second PMOS transistor 2021 and a second NMOS transistor 2022;
[0111] The acquisition tube 203 is composed of a third NMOS transistor 2031 and a fourth NMOS transistor 2032; the source of the third NMOS transistor is connected to the output terminal of the first inverter and the input terminal of the second inverter , the gate is connected to the word line WL of the memory, and the drain is connected to the bit line BL of the memory; the source of the fourth NMOS transistor is connected to the output terminal of the second inverter and the first inverter The gate is connected to the word line of the mem...
Embodiment 2
[0126] This embodiment adopts basically the same technical solution as Embodiment 1, the difference is that in Embodiment 1, for the NMOS transistor used in the inverter, the first heavily doped P-type region 2042 surrounds the first The vertical ends and lateral outer ends of a heavily doped N-type region 2041, the bottom of the first heavily doped N-type region 2041 is still in contact with the BOX, and a little leakage may still occur. The same is true for the PMOS transistors used in the inverters. In this embodiment, for the NMOS transistor used in the inverter, the first heavily doped P-type region 2042 not only surrounds the vertical ends and lateral outer ends of the first heavily doped N-type region 2041, but also further surrounds The bottom of the first heavily doped N-type region 2041; for the PMOS transistor used by the inverter, the second heavily doped N-type region surrounds both vertical ends and lateral outer ends of the second heavily doped P-type region , ...
Embodiment 3
[0129] The present invention also provides a method for making an SOI single-port SRAM unit, comprising the following steps:
[0130] Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.
[0131] As an example, such as Figure 15 As shown, four active regions 20a, 20b, 20c, and 20d are defined. These four active regions are arranged in parallel in turn, and shallow trenches are formed around each active region, and the shallow trenches are filled with insulating materials to form shallow trenches. isolation structure. In this embodiment, the insulating material is silicon dioxide.
[0132] Then execute step S2: as Figure 16 As shown, an N well 30, a first P well 40a, and a second P well 40b are fabricated in the top layer silicon according to the position of t...
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