Transverse insulated gate bipolar transistor
A technology of bipolar transistors and insulated gates, applied in the direction of transistors, diodes, and electric solid-state devices, can solve problems such as increasing the forward conduction voltage drop, weakening the conductance modulation effect in the drift region, and unfavorable practical applications of devices, etc., to achieve fast switching The effects of high break-down speed, high breakdown voltage and low turn-off loss
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Embodiment 1
[0030] Such as image 3 As shown, the schematic diagram of the structure of this example includes a substrate 1, an insulating layer 2 and an N-type low-doped drift region 3 stacked from bottom to top; the upper layer of the N-type low-doped drift region 3 has two sides respectively P-type body region 4 and N-type buffer region 7, the upper layer of said P-type body region 4 has P+ contact region 6 and N+ emitter region 5 arranged side by side, wherein N+ emitter region 5 is located on the side close to N-type buffer region 7 The N-type buffer area 7 has a P-type collector region 8; the upper surface of the P+ contact region 6 and part of the N+ emitter region 5 has an emitter metal electrode 130, and the upper surface of the P-type body region 4 has a first A gate structure, the first gate structure is composed of a first gate dielectric layer 110 and a first polysilicon gate electrode 120 located on the upper surface of the first gate dielectric layer 110, and the lower surfac...
Embodiment 2
[0037] Such as Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that compared with Embodiment 1, in this embodiment, the P-type collector region 8 and the collector metal electrode 131 and the highly doped N+ region 9, the highly doped P+ region 10 and The position of the third metal electrode 134 is interchanged. Therefore, in this example, the P-type collector region 8 is closer to the P-type body region 4 than the N+ region 9 and P+ region 10; compared with Example 1, the P-type collector region 8 and the N-type low-doped drift region are reduced. The thickness of the equivalent N-type buffer layer 7 between 3 and 3 further reduces the conduction loss of the device.
Embodiment 3
[0039] Such as Figure 5 As shown, in this embodiment, compared with Embodiment 2, a Zener diode is directly formed in the polysilicon layer above the dielectric layer 112. The Zener diode and the polysilicon diode share a highly doped N+ region 123, and the highly doped N+ region 123 is The anode of the Zener diode, the polysilicon N+ region 126 is the cathode of the Zener diode, and the polysilicon P+ region 125 is the highly doped region between the anode and cathode of the Zener diode; meanwhile, the Zener diode type in the polysilicon layer above the dielectric layer 112 , The position and shape can be adjusted as required, for example, the N + region 126 and P + region 125 can be arranged in the width direction of the device perpendicular to the horizontal direction; compared with embodiment 2, the integration is improved and the chip area is reduced.
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