Flash memory unit structure forming method

Abstract

The invention provides a flash memory unit structure forming method. The method comprises the following steps: device ion implantation is carried out to form a substrate structure; a flash memory oxide layer, a floating gate polysilicon layer, a silicon oxide layer and a silicon nitride layer are deposited sequentially on the above structure; a shallow trench isolation structure is formed on the above structure; liner silicon oxide pre-cleaning is carried out on the above structure, part of the silicon oxide layer is removed, and a floating gate polysilicon sharp point is exposed; a liner silicon oxide layer is formed in the shallow trench structure of the above structure, the exposed floating gate polysilicon sharp point is oxidized, and the sharp point is smooth; the silicon oxide isolation is deposited in the shallow trench and is etched; and the silicon nitride layer is etched and removed until the floating gate polysilicon layer is exposed. According to the flash memory unit structure forming method provided by the invention, the process integration problem of a 45-nanoscale flash memory unit is solved, and the flash memory unit with floating gate sharp point rounding and floating gate surface non damage can be acquired.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for forming a flash memory unit structure. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells with high-node technologies. It means that the size of the flash memory unit needs to be reduced. The reduction of the active area width and channel length of the flash memory unit according to the original structure will affect the mutual i...

AI Technical Summary

Problems solved by technology

[0005] Disadvantages: After silicon nitride is removed, the flash memory area is opened to remove silicon oxide, which affects the surface of the floating gate, and the uniformity of the surface oxidation becomes worse after removal (because the floating gate is polysilicon, the grain boundary has a greater impact)

[0008] Disadvantages: The sharp corners of the floating gate cannot be exposed because the silicon nitride has not been removed, resulting in the sharp corners of the floating gate not being rounded, and the subsequent high electric field is easy to accumulate, and there is a risk of charge loss

[0009] These two methods cannot simultaneously realize the rounding of the corners of the floating gate and the problem that the top of the floating gate of the flash memory is damaged by dry etching

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