Charge transfer type sense amplifier

Abstract

The invention discloses a charge transfer type sense amplifier. The charge transfer type sense amplifier comprises a compensating circuit unit, wherein the compensating circuit unit is connected between a power supply voltage and a column data line node for providing a compensating current; the compensating circuit unit has a structure that the compensating current can self-adaptively change basedon a voltage of the column data line node; when a memory unit is in a programming state, a pull-down current of the memory unit for the column data line node is reduced, the column data line node isrequired to reach a high potential, the higher the voltage of the column data line node is, the larger the compensating current is, and the larger the compensating current is, the higher the rate at which the column data line node rises to a target value is; and when the memory unit is in an erasing state, the pull-down current of the memory unit for the column data line node is increased, the column data line node is required to reach a low potential, the lower the voltage of the column data line node is, the smaller the compensating current is, and the smaller the compensating current is, the higher the rate at which the column data line node drops to the target value is. The charge transfer type sense amplifier disclosed by the invention can increase a change rate of the column data line node, thereby increasing a reading rate.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge transfer type sensitive amplifier. Background technique [0002] Such as figure 1 Shown is the circuit diagram of the existing charge transfer type sense amplifier; the existing charge transfer type sense amplifier includes: [0003] The gate of the NMOS transistor n101 is connected to the clamping voltage VCLAMP and kept in an on state; the source is connected to the bit line node B1 and connected to the memory unit (cell) 102 through the bit line node B1. [0004] The source of the PMOS transistor p101 is connected to the power supply voltage VDD, the drain is connected to the drain of the NMOS transistor n101 and both are connected to the column data line node VD, the gate of the PMOS transistor p101 is connected to the control signal PBIAS, and PBIAS is a fixed voltage, such as through the current mirror the bias voltage. [0005] The non-inverting input of th...

AI Technical Summary

Problems solved by technology

The disadvantage of this setting is: the compensation current is beneficial to reading p cell, and the VD voltage will not drop; but it is unfavorable to reading e cell, which will cause the VD voltage to drop slowly and reduce the reading speed

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