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Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

A punch-through-stop, semiconductor technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve problems such as subsequent diffusion of dopants

Active Publication Date: 2018-03-06
ATOMERA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, a potential problem with deterministic doping is the subsequent diffusion of dopants, making room temperature stability very challenging.

Method used

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  • Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
  • Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
  • Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

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Embodiment Construction

[0025] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Many different forms may, however, be implemented based on the teachings set forth herein, and the disclosure should not be construed as limited to the specific example embodiments provided. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosed concept to those skilled in the art. Like reference numerals refer to like elements throughout, and primary symbols are used to indicate similar elements in different embodiments.

[0026] Applicants state theoretically (but without wishing to be bound thereto) that the particular superlattice described herein reduces the effective mass of charge carriers and that this in turn leads to higher charge carrier mobility. In the literature, various definitions are used to describe effective mass. As an impro...

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Abstract

A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.

Description

technical field [0001] The present disclosure relates generally to semiconductor devices, and more particularly, to enhancement materials and dopant implantation techniques for semiconductor devices. Background technique [0002] Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, US Patent Application No. 2003 / 0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also includes impurity-free regions that would otherwise cause performance degradation. The biaxial strain created in the upper silicon layer alters carrier mobility, allowing higher speed and / or lower power consumption devices. Published US Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses CMOS inverters also based on similar strained silicon technology. [0003] US Patent No. 6,472,685 B2 to Takagi discloses a semiconductor...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L27/092H01L29/06H01L29/10H01L29/15H01L29/423H01L29/66H01L29/78H01L21/8234H01L21/8238
CPCH01L21/823412H01L21/823493H01L21/823807H01L21/823892H01L27/088H01L27/092H01L27/0922H01L29/0638H01L29/1045H01L29/105H01L29/1054H01L29/1083H01L29/152H01L29/155H01L29/157H01L29/158H01L29/42384H01L29/66537H01L29/7833
Inventor R·J·梅尔斯武内英树
Owner ATOMERA INC
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