Offset voltage self-adaptive digital calibration type sense amplifier

Abstract

The invention discloses an offset voltage self-adaptive digital calibration type sense amplifier, which is a sense amplifier circuit structure capable of effectively lowering offset voltage. The structure utilizes a simple peripheral circuit to realize the calibration compensation of the offset voltage of the sense amplifier and a compensation state latching operation, and a purpose of lowering the offset voltage to a large extent is achieved. Meanwhile, since the offset voltage is lowered, the design margin of a static random access memory reading circuit is effectively improved so as to lower power consumption generated when a unit is read, and the data reading speed of the static random access memory is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an offset voltage adaptive digital calibration type sensitive amplifier. Background technique [0002] With the rapid development of the integrated circuit industry in recent years, the high-speed and low-power characteristics of Static Random Access Memory (SRAM) play an increasingly important role in circuit design. The read operation of SRAM requires more For a long time, in order to improve the performance of SRAM, a sense amplifier (Sense Amplifier, abbreviated as SA) is usually used in the data readout path. Under ideal conditions, only a small voltage difference needs to be input, and the sense amplifier can feedback the logic. "0" and "1". However, due to the fluctuation of process parameters, device parameters such as transconductance and threshold voltage are mismatched. For SA, an offset voltage will be generated, which will cause small swing input signals to ...

AI Technical Summary

Problems solved by technology

Compared with the traditional voltage type SA, this structure has four different combinations. Under the condition of selecting the best combination, the structure has better anti-offset voltage capability, but the logic judgment of the best combination of the circuit is more complicated

[0004] (2) if image 3 Shown is the Robust Latch-Type SA circuit designed by T.Song and S.M.Lee in 2010. This design is used to reduce the influence of leakage current and offset voltage, and improve the accuracy of SA reading data, but this The circuit design does little to reduce the offset voltage, while extending the operating time of the SA and reducing the speed of the SA

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