3d NAND detection structure and its formation method
A detection structure, stacking structure technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of not being able to quickly and timely obtain 3D NAND detection results, prolong the cycle of 3D NAND development and market launch, and shorten the performance detection cycle , save time and cost, and simplify the process steps
Active Publication Date: 2019-03-01
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
Therefore, the test results of 3D NAND cannot be obtained quickly and timely, which prolongs the development and market launch cycle of 3D NAND
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[0025] The specific implementation of a 3D NAND detection structure and its forming method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0026] Please refer to figure 1 , is a structural schematic diagram of a method for forming a 3D NAND detection structure in a specific manner of the present invention.
[0027] The formation method of described 3D NAND detection structure comprises the steps:
[0028] Step S101: Provide a semiconductor substrate, the surface of the semiconductor substrate is formed with a stack structure and a dielectric layer surrounding the stack structure, the stack structure is formed by stacking a sacrificial layer and an isolation layer, including a core region and surrounding the core In the stepped area of the region, the dielectric layer covers the stacked structure.
[0029] Step S102: forming a gate via hole penetrating through the core region to the surface of the semiconduc...
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The present invention relates to a 3D NAND test structure and a forming method thereof, the forming method comprising: providing a semiconductor substrate, a stack structure and a dielectric layer surrounding the stack structure are formed on the surface of the semiconductor substrate, the stack structure is composed of a sacrificial Layers and isolation layers are stacked, including a core area and a stepped area surrounding the core area, the dielectric layer covers the stacked structure; forming gate via holes penetrating the core area to the surface of the semiconductor substrate; removing all The sacrificial layer, forming openings between the isolation layers; forming the control gates filling the openings and the first metal plugs filling the gate through holes, the first metal plugs are connected with each layer The control gate is electrically connected. The 3D NAND test structure formed by the above method short-circuits all control gates through the first metal plug, so that all memory cells can be tested only through the first metal plug.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a 3D NAND detection structure and a forming method thereof. Background technique [0002] With the continuous development of 3D NAND technology, the storage structure of 3D NAND has exceeded 64 layers, and the parallel development of memory array chips and peripheral CMOS circuit chips will help to further improve development efficiency. Even memory array chips of different generations can share similar CMOS circuit chips to achieve higher storage capacity and memory cell density. [0003] In addition to basic research related to the process, how to quickly perform read testing is very important when the technology node reaches a higher generation. At present, the reading and testing process of 3D NAND memory is mainly divided into three stages: the first stage is to read the switching current of the memory cell through a semi-manual nanoprobe; the second stage is to pass...
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IPC IPC(8): H01L27/115G01R31/26H10B69/00
CPCG01R31/2637H10B41/35H10B41/20
Inventor 肖莉红张勇戴晓望李思晢汤召辉周玉婷
Owner YANGTZE MEMORY TECH CO LTD